ICL7112 데이터 시트보기 (PDF) - Intersil
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ICL7112 Datasheet PDF : 14 Pages
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ICL7112
Pin Descriptions
PIN NO.
NAME
DESCRIPTION
1
No connection.
2
AGNDf
FORCE input for analog ground.
3
CS
Chip Select enables reading and writing (active low).
4
RD
ReaD (active low).
5
A0
Byte select (low = D0 -D7, high = D8 -D11, OVR).
6
BUS
Bus select (low = outputs enabled by A0, high = all outputs enabled together).
7
DGND
Digital GrouND return.
8
D11
Bit 11 (most significant bit).
9
D10
Bit 10
10
D9
Bit 9
11
D8
Bit 8
High Byte
12
D7
Bit 7
13
D6
Bit 6
14
D5
Bit 5
15
D4
Bit 4
Output
Data
Bits
(High =True)
16
D3
Bit 3
17
D2
Bit 2
Low Byte
18
D1
Bit 1
19
D0
Bit 0 (least significant bit).
20
No connection.
21
No connection.
22
No connection.
23
No connection.
24
No connection.
25
EOC
End of conversion flag (low = busy, high = conversion complete).
26
OVR
OVerRange flag (valid at end of conversion when output code exceeds full-scale;
three-state output enabled with high byte).
27
V+
Positive power supply input.
28
PROG
Used for programming only. Must tie to V+ for normal operation.
29
TEST
Used for programming only. Must tie to V+ for normal operation.
30
OSC1
Oscillator inverter input.
31
OSC2
Oscillator inverter output.
32
TEST
Must tie to V+ for normal operation.
33
WR
WRite pulse input (low starts new conversion).
34
CAZ
Auto-zero capacitor connection (Note).
35
V-
Negative power supply input.
36
COMP
Used in test, tie to V-.
37
VIN
SENSE line for input voltage.
38
VREF
SENSE line for reference input.
39
AGNDs
SENSE line for analog ground.
40
No connection
NOTE: The voltage of CAZ is driven; NEVER connect directly to ground.
6-5
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