80C86 데이터 시트보기 (PDF) - Intersil

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80C86

CMOS 16-Bit Microprocessor

Intersil 

Waveforms (Continued)

AC Test Circuit

80C86

≥ 50µs

VCC

CLK

(7) TCLDX1

(6) TDVCL

RESET

≥ 4 CLK CYCLES

FIGURE 13. RESET TIMING

OUTPUT FROM

DEVICE UNDER TEST

TEST POINT

CL (SEE NOTE)

NOTE: Includes stay and jig capacitance.

AC Testing Input, Output Waveform

INPUT

VIH + 20% VIH

1.5V

VIL - 50% VIL

OUTPUT

1.5V

VOH

VOL

NOTE: AC Testing: All input signals (other than CLK) must switch between VILMAX -50% VIL and VIHMIN +20% VIH. CLK must switch between 0.4V

and VCC. - 0.4 Input rise and fall times are driven at 1ns/V.

28

FN2957.3

January 9, 2009

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