IDT7130SA100F 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7130SA100F

HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM

Integrated Device Technology 

IDT7130SA/LA and IDT7140SA/LA

High-Speed 1K x 8 Dual-Port Static SRAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)

ADDR

'A' AND 'B'

ADDRESSES MATCH

CE'B'

CE'A'

BUSY'A'

tAPS(2)

tBAC

tBDC

2689 drw 14

Timing Waveform by BUSY Arbitration Controlled

by Address Match Timing(1)

ADDR'A'

ADDR'B'

tAPS(2)

tRC OR tWC

ADDRESSES MATCH

ADDRESSES DO NOT MATCH

BUSY'B'

tBAA

tBDA

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7130 only).

2689 drw 15

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(2)

7130X20(1)

7140X20(1)

Com'l Only

7130X25

7140X25

Com'l, Ind

& Military

Symbol

Parameter

Min. Max. Min. Max.

INTERRUPT TIMING

tAS

Address Set-up Time

0

____

0

____

tWR

Write Recovery Time

0

____

0

____

tINS

Interrupt Set Time

____

20

____

25

tINR

Interrupt Reset Time

____

20

____

25

NOTES:

1. PLCC, TQFP and STQFP package only.

2. 'X' in part numbers indicates power rating (SA or LA).

7130X35

7140X35

Com'l

& Military

Min. Max. Unit

0

____

ns

0

____

ns

____

25

ns

____

25

ns

2689 tbl 12a

14

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