IDT72V71660 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72V71660

3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 X 16,384

Integrated Device Technology 

IDT72V71660 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 16,384 x 16,384

INDUSTRIAL TEMPERATURE RANGE

PIN DESCRIPTION

SYMBOL

NAME

A0-15 Address 0 to 15

CLK

Clock

CS

D0-15

DS

Chip Select

Data Bus 0-15

Data Strobe

DTA

Data Transfer

Acknowledgment

FE/HCLK Frame Evaluation/

HCLK Clock

I/O DESCRIPTION

I These address lines access all internal memories.

I Serial clock for shifting data in/out on the serial data streams. Depending upon the value programmed, this

input accepts a 4.096, 8.192 or 16.384 MHz clock. See the Control Register bits on Table 5 for the values.

I This active LOW input is used by a microprocessor to activate the microprocessor port of IDT72V71660.

I/O These pins are the data bits of the microprocessor port.

I This active LOW input works in conjunction with CS to enable the read and write operations and enables the

data bus lines (D0-D15).

O Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then goes

high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required

to hold a HIGH level when the pin is in high-impedance.

I When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the

HCLK (4.096 MHZ clock) is required for frame alignment in the wide frame pulse mode (WFPS). (1)

FP

Frame Pulse

I WhentheWFPSpinisLOW,thisinputacceptsandautomaticallyidentifiesframesynchronizationsignals

formatted according to ST-BUS® and GCI specifications. When pin WFPS is HIGH, this pin accepts a

negative frame pulse, which conforms to the WFPS format.

GND Ground

Ground Rail.

ODE Output Drive Enable

RESET Device Reset

I This is the output enable control for the TX serial outputs. When the ODE input is LOW and the Output Stand

By bit of the Control Register is LOW, all TX outputs are in a high-impedance state. If this input is HIGH, the TX

output drivers are enabled. However, each channel may still be put into a high-impedance state by using the

per-channel control bit in the Connection Memory.

I This input puts the IDT72V71660 into a reset state that clears the device internal counters, registers and

brings TX0-63 and D0-D15 into a high-impedance state. The RESET pin must be held LOW for a

minimum of 20ns to properly reset the device.

R/W

Read/Write

I This input controls the direction of the data bus lines (D0-D15) during a microprocessor access.

RX0-63 DataStream

Input 0 to 63

I Serial data input stream. These streams may have a data rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, or

16.384Mb/s, depending upon the value programmed in the Control Register.

TCK TestClock

I Provides the clock to the JTAG test logic.

TDI

Test Serial Data In

I JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up

when not driven.

TDO Test Serial Data Out

O JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state

when JTAG scan is not enabled.

TMS Test Mode Select

I JTAG signal that controls the state transitions of the Test Access Port controller. This pin is pulled HIGHby an

internal pull-up when not driven.

TRST TestReset

I AsynchronouslyinitializestheJTAGTestAccessPortcontrollerbyputtingitintheTest-Logic-Resetstate.This

pin is pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,

to ensure that the IDT72V71660 is in the normal functional mode.

TX0-31 TX Output 0 to 31

(Three-state Outputs)

O Serial data output stream. These streams may have a data rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s,

or 16.384Mb/s, depending upon the value programmed in the Control Register.

TX32-63/ TX Output 32 to 63/

OEI0-31 OutputEnable

Indication 0 to 31

(Three-state Outputs)

O Whenall64outputstreamsareselectedviaControlRegister,thesepinsaretheoutputstreamsTX32toTX63

and may operate at a data rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, or 16.384Mb/s. When output enable

function is selected, these pins reflect the active or high-impedance status for the

corresponding outputstreamOEI0-31.

VCC

VCC

+3.3 Volt Power Supply.

WFPS

Wide Frame Pulse Select I When 1, enables the wide frame pulse (WFPS) Frame Alignment interface. When 0, the device operates in

ST-BUS® /GCI mode.(2)

NOTES:

1. For compatibility with the IDT72V73273/63 device, this pin should be logic High.

2. For compatibility with the IDT72V73273/63 device, this pin should be logic Low.

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