Preliminary Specification
IMT
ADDRESS
DQ
CE
OE
WE
SIX-BYTE COMMAND CODE FOR PAGE ERASE OPERATION
5555
2AAA
5555
5555
2AAA
Page Address
AA
55
80
AA
55
30
t WP
t WC
t WPH
t WHWH2
Internal Erase Start
Fig. 5 Page Erase Timing Diagram
ADDRESS
DQ
CE
OE
WE
SIX-BYTE COMMAND CODE FOR CHIP ERASE OPERATION
5555
2AAA
5555
5555
2AAA
5555
AA
55
80
AA
55
10
t WP
t WC
t WPH
t WHWH3
Internal Erase Start
Fig. 6 Chip Erase Timing Diagram
This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27
Integrated Memory Technologies, Inc.
2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696