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IM29LV001B 데이터 시트보기 (PDF) - Unspecified

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IM29LV001B Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Preliminary Specification
IMT
Flexible Boot Block Architecture
The page erase function of IM29LV001T/B
erases only the bytes located inside the 512-
byte boundary (as defined by A9 - A16) of
the selected page. It does not affect any
other memory location outside of the page
boundary. Any page of the array can be
used as an independent data storage unit
which is not affected by the erase and
programming operations of the rest of the
array. A boot block of any size can be
constructed by selecting a contiguous, or
non-contiguous if so desired, group of pages
from the top or bottom address. This
provides the most convenient boot block
configuration than those utilizing the fixed-
size boot block approach.
Hard Wired Data Protection
A hard wired data protection option is
provided for the first 32 pages either from the
top address (IM29LV001T) or from the
bottom address (IM29LV001B). This option
can be utilized to protect the BIOS boot
codes which
usually reside in the top or bottom 16K-byte
address range.
Device Operation
Read
The read operation of the IM29LV001T/B is
activated by setting CE# and OE# to low
(VIL) and WE# to high (VIH). Data is obtained
from the output pins. CE# controls the device
selection function. When CE# is high, the
device is deselected and only standby power
is consumed. When CE# is low, the device is
selected. OE# controls the output buffer. It is
used to gate data from the output pins. The
data bus is in high impedance state when
either CE# or OE# is high. See Fig. 1 for the
read cycle timing diagram.
Write
The write operation is used to issue
commands and data for the program and
erase functions of the device. It is initiated by
forcing CE# low, OE# high and WE# low.
The addresses are latched by the falling
edge of either CE# or WE#, whichever
occurs last. The data is latched by the rising
edge of either CE# or WE#, whichever
occurs first. See Fig. 2 for the timing diagram
of writing a command with WE# as the
controlling signal, and Fig. 3 for that with
CE# as the controlling signal.
Erase: Page and Chip Erase
The IM29LV001T/B provides two erase
functions: page erase and chip erase. The
page erase function erases a single page
(512 bytes in size) at a time. It is activated by
writing the page erase command to the part.
The page erase command is consisted of 6
write cycles as shown in Table 2. The first 5
cycles contain the command codes, while
the 6th cycle asserts the page address (A9 to
A16) by forcing the correct address signals
to the address pins. See Fig. 9 for the flow
chart and Fig. 5 for the page erase timing
diagram. The chip erase function erases the
complete 1 mega-bit array simultaneously. It
is activated by a 6-byte command cycle
shown in Table 2. See Fig. 6 for the timing
diagram and Fig. 10 for the flow chart.
The page and chip erase operations, once
initiated, will trigger an internal timer to start
the erase operation until completion, which
takes typically 6 ms for the page and 2 sec
for the chip erase. During this period, the
data and address buses of the part are in
high impedance states. The system buses
Read
Standby
OPERATION
CE#
VIL
VIH
OE#
VIL
X
WE#
VIH
X
A0
A Note 1
in
X
Output Disable
Write
Enable Hardwired Data Protect
Disable Hardwired Data Protect
Verify Hardwired Data Protect
VIL
VIH
VIH
VIL
VIH
VIL
VIL
VH Note 1
VIL
VH
VH Note 1
VIL
VIL
VIL
VIH
X
A Note 1
in
X
X
VIL
Product Identification
Manufacturer ID Byte 1 VIL
VIL
VIH
VIL
Byte 2 VIL
VIL
VIH
VIH
Device ID
VIL
VIL
VIH
VIH
Note 1: VH=12 V, Ain = address input, X = don’t care.
Note 2: A5H for IM29LV001T and A6H for IM29LV 001B
Table 1 Operation Modes
A1
A Note 1
in
X
X
A Note 1
in
X
X
VIH
VIL
VIH
VIL
A9
A Note 1
in
X
X
A Note 1
in
VH Note 1
VH Note 1
VH Note 1
VH Note 1
VH Note 1
VH Note 1
I/O
DOUT
HIGHZ
HIGHZ
DIN
X
X
CODE
7FH
1FH
A5H/A6HNote 2
This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27
Integrated Memory Technologies, Inc.
2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696

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