IP2004TR 데이터 시트보기 (PDF) - International Rectifier

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IP2004TR

SYNCHRONOUS BUCK LGA POWER BLOCK

International Rectifier 

Data Sheet No. PD60322

iP2004

Figure 15 Top & Bottom Component and Via Placement (Topside, Transparent view down)

PCB Layout Guidelines

The following guidelines are recommended to reduce the parasitic values and optimize overall performance.

• All pads on the iP2004 footprint design need to be Solder-mask defined (see Figure 14). Also refer to

International Rectifier application notes AN1028 and AN1029 for further footprint design guidance.

• Place as many vias around the Power pads (VIN, VSW, and PGND) for both electrical and optimal thermal

performance.

o Vias in between the different power pads may overlap the pad opening and solder mask edge

without the need to plug the via hole. Vias with a 13mil drill hole and 25mil capture pad were

used in this example.

• A minimum of six 10µF, X5R, 16V ceramic capacitors per iP2004 are needed for greater than 25A

operation. This will result in the lowest loss due to input capacitor ESR.

• Placement of the ceramic input capacitors is critical to optimize switching performance. In cases where

there is a heatsink on the case of iP2004, place all six ceramic capacitors right underneath the iP2004

footprint (see Bottom Component Layer). In cases where there is not heatsink, C1 and C6 on the

bottom layer may be moved to the C1x and C6x locations (respectively) on the top component layer

(see Top Component Layer). In both cases, C2 – C5 need to be placed right underneath the iP2004

PCB footprint.

• Dedicate at least two layer to for PGND only

• Duplicate the Power Nodes on multiple layers (refer to AN1029).

Page 12 of 15

www.irf.com

12/22/2007

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