IR3092MTR 데이터 시트보기 (PDF) - International Rectifier
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IR3092MTR Datasheet PDF : 37 Pages
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IR3092
IR3092 THEORY OF OPERATION
VC C
LGND
SETBIAS
4 X IROSC
BIASOUT
5VUVL
PW R GD
U VL
-
+
7.8V START
7.3V STOP
UVL
-
+
4.300V START
4.125V STOP
I OVP
ON
OVP
45k
ROSC
I R OSC
FB
IROSC
1. 243
CLK1
CLK2
Os c illat or
OVP Comparator
BB DISABLE COMPARATOR
FB
AMD=450mV
I N TEL=150m V
80mV
VDAC
I R OSC
EAOUT
PWM COMPARATOR
RESET DOMINANT
S
Q
QB
R
RSFF
I R OSC / 2
10p
0.7V
0% DUTY CYCLE
IN
GATEHI
OL_IN OL_OUT
GateHI
OL_IN OL_OUT
IN
GATELO
GateLO
VDAC
OVER CURRENT
0.55V
OC SET
IROSC
DELAY
-
+
240mV chrg, 210mV dischrg
1.3V
Sof tStart_Clamp
+
-
DI SABLE
Error_Amp
4V
OFF
55U
SS
5.5U
ON
45U
3V
EN ABLE
AMD =1. 5V
INTEL=0.6V
VI D _SEL
15k
-
+
VOSNS-
3.4V
60K
- Discharge Comparator
+
0.26V
1.9us
BLAN KI N G
4.9V
5V
3.3V
1
110K
18uA
EQUAL DUTY CY CLE COMPARATOR
FAULT LATCH
S
-
+
0.7V
R
SET DOMINANT
DAC DEFAULTS TO VR10
WITH VID_SEL GROUNDED
F11111
DAC
ATH LON _D AC
OPTERON_DAC
OUT
FAST DAC
DAC BUFFER
-
+
IROSC
PWM COMPARATOR
H FORCES IROSC/2 AT SS<0.7V
RESET DOMINANT
S
Q
QB
R
RSFF
IROSC
0 TO IROSC*3/4
0.7V
10p
Share Adjust Error Amp
+
-
X25
s um m er
VDAC
s um m er
X25 -
+
IN
GATEH I
OL_IN OL_OUT
Gat eH I
VC C L
U 18
OL_IN OL_OUT
IN
GATELO
GateLO
1.2V
VID0
VID1
VI D 2
VI D 3
VID4
VID5
VOSNS-
VDAC
VCCH1
GATEHI 1
VCCL
GATEL1
PGND1
C SI N P1
C SI N M
C SI N P2
VDRP
SCOMP
VCCH2
GATEH2
GATEL2
PGND2
Figure 1 – IR3092 Block Diagram
PWM Operation
The IR3092 is a fully integrated 2 phase interleaved PWM control IC which uses voltage mode control with trailing edge
modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the control IC is used for the voltage control loop.
The PWM block diagram of the IR3092 is shown in Figure 2.
Refer to Figure 3. Upon receiving a clock pulse, the RSFF is set, the internal PWM ramp voltage begins to increase, the
low side driver is turned off, and the high side driver is then turned on. For phase 1, an internal 10pf capacitor is charged
by a current source that’s proportional to the switching frequency resulting in a ramp rate of 57mV per percent duty cycle.
For example, if the steady-state operating switch node duty cycle is 10%, then the internal ramp amplitude is typically
570mV from the starting point (or floor) to the crossing of the EAOUT control voltage. When the PWM ramp voltage
exceeds the Error Amplifier’s output voltage, the RSFF is reset. This turns off the high side driver, turns on the low side
driver, and discharges the PWM ramp to 0.7V until the next clock pulse.
Page 10 of 37
06/25/04
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