IR3092M 데이터 시트보기 (PDF) - International Rectifier
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IR3092M Datasheet PDF : 37 Pages
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IR3092
R OSC
C D AC
R D AC
R OSC
VDAC
U39
IROSC
CLK1
CLK2 CLK2
OSC BLOC K
80mV
R SF F
S
PWM COMPARATOR
-
QB
R
+
RESET DOMINANT
BB DISABLE
-
+
I R OSC / 2
10p
0.7V
VOSN S-
VDAC
ERROR AMPLIFIER
FB
C C OMP
R C OMP
EAOU T
IROSC
RDRP VDRP
VDRP BUFFER
RFB
SCOMP
C SC 2
0.55V
0% DUTY CY CLE
R SF F
C LK2
S
PWM COMPARATOR
-
QB
R
+
RESET DOMINANT
IROSC
Share Adjust Error Amp
+
10p
-
0 TO IROSC*3/4
0.7V
VDAC
R SC 2
VDAC
X24.5 -
+
X24.5 -
+
GATEH1
VIN
GATEL1
1
2
RCS1 CCS1
GATEH2
GATEL2
VIN
1
2
RCS2 CCS2
C SI N P2
C SI N M
C SI N P1
VOUT SENSE+
VOU T+
COUT
VOU T-
VOUT SENSE-
Figure 2 – PWM Block Diagram
The RSFF is reset dominant allowing both phases to go to zero duty cycle within a few tens of nanoseconds in response
to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on
gated by the clock pulses. An Error Amplifier output voltage greater than the common mode input range of the PWM
comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the
Error Amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load
step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will
increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response” where the inductor current changes in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing
the output capacitor requirements.
Page 11 of 37
06/25/04
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