IR3093MTR 데이터 시트보기 (PDF) - International Rectifier
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IR3093MTR Datasheet PDF : 39 Pages
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IR3093
PWM Operation
The IR3093 is a fully integrated 3 phase interleaved PWM control IC which uses voltage mode control with trailing
edge modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the Control IC is used for the voltage
control loop. The PWM block diagram of the IR3093 is shown in Figure 2.
CDAC
RDAC
OVPSNS
VDAC
U30
IROSC
CLK1
CLK2 CLK2
CLK3 CLK3
OSCBLOCK
80mV
BB DISABLE
VOSNS-
VDAC
ERROR AMPLIFIER
PWM COMPARATOR
-
+
RSFF
S
Q
QB
R
RESET DOMINANT
I R OSC / 2
9p
0.6V
FB
CCOMP
RCOMP
EAOUT
IROSC
RDRP VDRP
VDRP BUFFER
RFB
SCOMP2
0. 47V
0% DUTY CYCLE
RSFF
CLK2
S
PWM COMPARATOR
Q
-
QB
R
+
RESET DOMINANT
IROSC
Share Adjust Error Amp
+
9p
-
0 TO IROSC*3/4
0.6V
CSC2
RSC2
RSFF
CLK3
S
PWM COMPARATOR
Q
EAOUT
-
QB
R
+
RESET DOMINANT
IROSC
SCOMP3
CSC3
RSC3
Share Adjust Error Amp
+
9p
-
0 TO IROSC*3/4
0.6V
VDAC
VDAC
VDAC
X23. 5
-
+
X23.5 -
+
X23.5 -
+
VIN
GATEH1
GATEL1
1
2
RCS1 CCS1
GATEH2
GATEL2
VIN
1
2
RCS2 CCS2
GATEH3
GATEL3
VIN
1
2
RCS3 CCS3
C SI NM3
C SI NP3
C SI NM2
C SI NP2
C SI NM1
C SI NP1
VOUT SENSE+
VOUT+
COUT
VOUT-
VOUT SENSE-
Figure 2 – PWM Block Diagram
Refer to Figure 3. Upon receiving a clock pulse, the RSFF is set, the internal PWM ramp voltage begins to increase,
the low side driver is turned off, and the high side driver is then turned on. For phase 1, an internal 9pf capacitor is
charged by a current source that proportional to the switching frequency resulting in a ramp rate of 50mV per percent
duty cycle. For example, if the steady-state operating switch node duty cycle is 10%, then the internal ramp amplitude
is typically 500mV from the starting point (or floor) to the crossing of the EAOUT control voltage. When the PWM
ramp voltage exceeds the Error Amplifier’s output voltage, the RSFF is reset. This turns off the high side driver, turns
on the low side driver, and discharges the PWM ramp to 0.6V until the next clock pulse.
Page 11 of 39
07/15/04
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