IR3093 데이터 시트보기 (PDF) - International Rectifier
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IR3093 Datasheet PDF : 39 Pages
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IR3093
PIN DESCRIPTION
PIN#
1
2
3
4
5
PIN SYMBOL
VID3
VID4
ROSC
VOSNS-
OCSET
6
VDAC
7
VDRP
8
FB
9
EAOUT
10
SS/DEL
11
SCOMP2
12
SCOMP3
13
LGND
14
SETBIAS
15
VCC
16
CSINP3
17
CSINM3
18
BIASOUT
19
PWRGD
20
CSINP2
21
CSINM2
22
VID_SEL
23
VCCL3
24
GATEL3
25
PGND3
26
GATEH3
27
VCCH3
28
VCCH2
29
GATEH2
30
PGND2
31
GATEL2
32
5VUVL
33
VCCL1_2
34
GATEL1
35
PGND1
36
GATEH1
37
VCCH1
38
NC
39
CSINM1
40
CSINP1
41
OVP
42
ENABLE
43
OVPSNS
44
5VREF
45
VID5
46
VID0
47
VID1
48
VID2
PIN DESCRIPTION
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET, BBFB, and VDAC bias currents
Remote Sense Input. Connect to ground at the Load.
Programs the hiccup over-current threshold through an external resistor tied to VDAC and an internal current
source.
Regulated voltage programmed by the VID inputs. Current Sensing and Over Current Protection are referenced
to this pin. Connect an external RC network to VOSNS- to program Dynamic VID slew rate.
Buffered IIN signal. Connect an external RC network to FB to program converter output impedance
Inverting input to the Error Amplifier. Converter output voltage is offset from the VDAC voltage through an
external resistor connected to the converter output voltage at the load and an internal current source. Bias
current is a function of ROSC. Also OVP sense
Output of the Error Amplifier
Controls Converter Softstart, Power Good, and Over-Current Timing. Connect an external capacitor to LGND to
program the timing.
Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s
bandwidth. Phase 2 is forced to match phase 1’s current.
Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s
bandwidth. Phase 3 is forced to match phase 1’s current.
Local Ground and IC substrate connection
External resistor to ground sets voltage at BIASOUT pin. Bias current is a function of ROSC.
Power for internal circuitry and source for BIASOUT regulator
Non-inverting input to the Phase 3 Current Sense Amplifier.
Inverting input to the Phase 3 Current Sense Amplifier.
200mA open-looped regulated voltage set by SETBIAS for GATE drive bias.
Open Collector output that drives low during Softstart or any fault condition. Connect external pull-up.
Non-inverting input to the Phase 2 Current Sense Amplifier.
Inverting input to the Phase 2 Current Sense Amplifier.
Ground Selects VR10.X VID, Float Selects OPTERON VID, VCC Selects ATHLON VID
Power for Phase 3 Low-Side Gate Driver.
Phase 3 Low-Side Gate Driver Output and input to GATEH3 non-overlap comparator.
Return for Phase 3 Gate Drivers
Phase 3 High-Side Gate Driver Output and input to GATEL3 non-overlap comparator.
Power for Phase 3 High-Side Gate Driver
Power for Phase 2 High-Side Gate Driver
Phase 2 High-Side Gate Driver Output and input to GATEL2 non-overlap comparator.
Return for Phase 2 Gate Drivers
Phase 2 Low-Side Gate Driver Output and input to GATEH2 non-overlap comparator.
Can be used to monitor the driver supply voltage or 5V supply voltage when converting from 5V. An under
voltage condition initiates Soft Start.
Power for Phase 1 and 2 Low-Side Gate Drivers.
Phase 1 Low-Side Gate Driver Output and input to GATEH1 non-overlap comparator.
Return for Phase 1 Gate Drivers
Phase 1 High-Side Gate Driver Output and input to GATEL1 non-overlap comparator.
Power for Phase 1 High-Side Gate Driver
Not connected
Inverting input to the Phase 1Current Sense Amplifier.
Non-inverting input to the Current Sense Amplifier.
Output that drives high during an Over-Voltage condition.
Enable Input. A logic low applied to this pin puts the IC into Fault mode.
Dedicated output voltage sense pin for Over Voltage Protection.
Compensation for internal voltage reference rail.
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Page 2 of 39
07/15/04
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