IS25F011A 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS25F011A

1M-BIT, 2M-BIT, AND 4M-BIT SERIAL FLASH MEMORIES WITH 4-PIN SPI INTERFACE

Integrated Silicon Solution 

IS25F011A

IS25F021A

IS25F041A

ISSI ®

AC ELECTRICAL CHARACTERISTICS

16 MHz (5V)

8 MHz (3V)

Symbol

tCYC

tWH

Description

SCK Serial Clock Period (1)

SCK Serial Clock High or Low Time

Min Typ Max

62 — —

26 — —

Min Typ Max

125 — —

57 — —

Unit

1 ns

ns

tWL

tRI

SCK Serial Clock Rise or Fall Time (2)

tFI

—— 3

—— 5

2 ns

tSU

Data Input Setup Time to SCLK

40 — —

100 — —

ns

tH

Data Input Hold Time from SCLK

tV

Data Output Valid after SCLK (1,3)

0 ——

— — 55

0 ——

— — 115

3 ns

ns

tLEAD

CS Setup Time to Command

100 — —

300 — —

ns

tLAG

CS Delay Time after Command

tWP

Erase/Write Program Time

100 — —

— 2.5 5

300 — —

— 5 10

ns

4 ms

(see Write to Sector Command)

tXP

Transfer Program-Buffer/SRAM

(see Transfer PB/SRAM Command)

tHD

SCK Setup Time to HOLD

— — 100

10 — —

— — 200

20 — —

µs

5

ns

tCD

SCK Hold Time from HOLD

30 — —

50 — —

ns

tCS

CS Deselect Time

tRB

READY / BUSY Valid Time

160 — —

160 — —

200 — —

200 — —

6 ns

ns

tDIS

Data Output Disable Time

— — 160

— — 200

ns

tHO

Data Output Hold Time

0 ——

0 ——

ns

7

Notes:

1. To achieve maximum clock performance, the read clock edge will need to be set for rising edge operation in the configuration

register (RCE=1).

2. Test points are 10% and 90% points for rise/fall times. All others timings are measured at 50% point.

3. With 50 pF (8 MHz) or 30 pF (16 MHz) load SO to GND.

8

9

10

11

12

Integrated Silicon Solution, Inc.

21

PRELIMINARY SF001-1A

06/24/98

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