IS25C128A
SERIAL INTERFACE DESCRIPTION
MASTER: The device that provides a clock signal.
SLAVE: The IS25C128A is a slave because the clock
signal is an input.
TRANSMITTER/RECEIVER: The IS25C128A has both
data input (SI) and data output (SO).
MSB: The most significant bit. It is always the first bit
transmitted or received.
OP-CODE: The first byte transmitted to the slave
following CS transition to LOW. If the OP-CODE is a
valid member of the IS25C128A instruction set (Table 3),
then it is decoded appropriately. If the OP-CODE is not
valid, and the SO pin remains in high impedance.
BLOCK DIAGRAM
STATUS
REGISTER
SI
CS
WP
SCK
DATA
REGISTER
MODE
DECODE
LOGIC
CLOCK
HOLD
VCC
GND
16K x 8
MEMORY ARRAY
ADDRESS
DECODER
OUTPUT
BUFFER
SO
Integrated Silicon Solution, Inc.
3
AdvancedInformation Rev. 00E
11/25/08