PRELIMINARY
KL5KUSB121
6.4 Serial EEPROM Byte Random Read
USB to 10/100 Ethernet Controller
Figure 6.4.1 SEP Byte Random Read Timings
SEPSCL
(OUT)
SEPSDA
(I/O)
status
(L)
(L)
(L)(7)(6)(5)(4)(3)(2)(1)(0)
idle
S 1 0 1 0 b2b1b0 0 Aa7a6a5a4a3a2a1a0 A S 1 0 1 0 b2b1b0 1 Ad7d6d5d4d3d2d1d0 N S
T control byte K word address K T control byte K read data KP
6.5 Serial EEPROM Sequential Read (up to final address)
Figure 6.5.1 SEP Sequential Read Timings
status
idle
S
T
cntrl w
Aw
K addrN
AS
KT
cntrl r
A
K
input
L input
L dat
N+1
L last in
H
S
P
(L)
(L)
(L) (dat N) AK(dat N+1)AK
AK
NK
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information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or
consequential damages. There are no warranties extended or granted by this document. The information herein is subject to change without notice
form Kawasaki LSI
February 22, 2000 • ©Copyright 2000 • Kawasaki LSI • Printed in U.S.A
Ver. 1.1
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
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