AD8347 데이터 시트보기 (PDF) - Analog Devices
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AD8347 Datasheet PDF : 20 Pages
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AD8347
Filter Design Considerations
Baseband low-pass or band-pass filtering can be conveniently
performed between the mixer outputs (IMXO/QMXO) and the
input to the baseband amplifiers. Because the output impedance
of the mixer is low (roughly 3 Ω) and the input impedance of
the baseband amplifier is high, it is not practical to design a
filter which is reactively matched to these impedances. An LC
filter can be matched by placing a series resistor at the mixer
output and a shunt resistor (terminated to VVREF) at the input to
the baseband amplifier.
Because the mixer output drive level is limited to a maximum cur-
rent of 1.5 mA, the characteristic impedance of the filter should be
greater than 50 Ω, especially if larger signal swings are to be achieved.
Figure 8 shows the schematic for a 100 Ω, fourth order elliptic
low-pass filter with a 3 dB cutoff frequency of 20 MHz. Source
and load impedances of approximately 100 Ω ensure that the
filter sees a matched source and load. This also ensures that the
mixer output is driving an overall load of 200 Ω. Note that the
shunt termination resistor is tied to VREF and not to ground.
The frequency response and group delay of this filter are shown
in Figures 9 and 10.
C1
4.7pF
C3
8.2pF
RS
L1 R3
L3 R4
95.3⍀ 0.68H 2⍀ 1.2H 2⍀
C2
150pF
C4 RL
82pF 100⍀
IMXO
AD8347
VREF
IAIN VDT1
(SEE
TEXT)
Figure 8. Typical Baseband Low-Pass Filter
0
–10
–20
–30
–40
–50
–60
–70
–80
1
10
100
FREQUENCY – MHz
Figure 9. Frequency Response of 20 MHz Baseband
Low-Pass Filter
50
45
40
35
30
25
20
15
10
5
0
1
10
100
FREQUENCY – MHz
Figure 10. Group Delay of 20 MHz Baseband Low-Pass
Filter
If the VGA is operating in AGC mode, the detector input (VDT1/
VDT2) can be tied either to the input or output of the filter.
Connecting the detector input to the input of the filter (i.e.,
IMXO and QMXO) will cause the VGA leveling point to be
determined by the composite of the wanted signal and any unfiltered
components such as blockers or signal harmonics. Connecting
VDT1/VDT2 to the outputs of the filters ensures that the leveling
point of the AGC circuit is based upon the amplitude of the
filtered output only. The latter option is more desirable as it
results in a more constant baseband output. However, when
using this method, the leveling point of the AGC should be set
so that out-of-band blockers do not overdrive the mixer output.
DC Offset Compensation
Feedthrough of the LO signal to the RF input port results in
self-mixing of the LO signal. This produces a dc component
at the mixer output that is frequency-dependent.
The AD8347 includes an internal circuit which actively nulls
out any dc offsets that appear at the mixer output. The dc-bias
level of the mixer output (which should ideally be equal to VVREF,
the bias level for the baseband sections of the chip) is continually
being compared to VVREF. Any differences between the mixer
output level and VVREF, will force a compensating voltage on to
the mixer output.
The time constant of this correction loop is set by the capacitors
which are connected to pins IOFS and QOFS (each output can
be compensated separately). For normal operation 0.1 µF capacitors
are recommended. The corner frequency of the compensation
loop is given approximately by the equation
( ) f = 40
3 dB COFS
COFS in µF
The corner frequency must be set to a frequency that is much
lower than the symbol rate of the demodulated data. This prevents
the compensation loop from falsely interpreting the data stream
as a changing offset voltage.
To disable the offset compensation circuits, IOFS and QOFS
should be tied to VREF.
REV. 0
–17–
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