L6360 데이터 시트보기 (PDF) - STMicroelectronics

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L6360

IO-Link communication master transceiver IC

STMicroelectronics 

L6360

Internal registers

Bit 7 = PO: Power-on (L+ line)

This bit indicates the status of L+ line voltage. If the voltage goes under the lower threshold (V LTHOFF ) and ENL+ is

high, the PO bit is set. It is reset after a successful current read if the L+ voltage has returned above the upper

threshold VLTHON and the read operation has begun after the bit has been set. When the PO bit is high, IRQ is

generated. During ENL+ transition (from low-level to high-level) and during L+ line voltage transition, a fault

condition is reported setting the PO bit and activating the IRQ pin. To reset the fault a successful current read is

necessary.

Figure 10. Power-on bit behavior

Current read

V L+

V THON

V TH OFF

VLHYST

PO

Bit 6 = not used: always at zero

Bit 5 = OVT: overtemperature fault

This bit indicates the status of the IC internal temperature. If the temperature goes above the thermal shutdown

threshold (T > TJSD) the OVT bit is set. It is reset after a successful current read if the temperature has returned

below the thermal restart threshold (TJDS - TJHIST) and the read operation has begun after the bit has been set.

When OVT bit is high, the power outputs are disabled and IRQ is generated.

Figure 11. Overtemperature (OVT) bit behavior

TJSD

TJRST

Current read

TJ

TJHYST

OVT

Bit 4 = CQOL: C/Q overload

This bit is set if a cut-off occurs on the C/Q channel. It is reset after a successful current read if the restart delay

time (trcoq) has elapsed or the protection is latched (bit trcoq = 1). The read operation should begin after the CQOL

bit has been set. When CQOL bit is high, IRQ is generated. When CQOL bit is high and the protection is latched

(bit trcoq = 1 in control register 1), the C/Q power output is disabled. See next figure.

DS8900 - Rev 7

page 17/63

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