LC4512C-10F256I 데이터 시트보기 (PDF) - Lattice Semiconductor

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LC4512C-10F256I

3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs

Lattice Semiconductor 

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 10. Global OE Generation for ispMACH 4032

Internal Global OE

PT Bus

(2 lines)

Global OE

4-Bit

Global OE Bus

Shared PTOE

(Block 0)

Shared PTOE

(Block 1)

Fuse connection

Hard wired

Global

Fuses

GOE (3:0)

to I/O cells

Zero Power/Low Power and Power Management

The ispMACH 4000 family is designed with high speed low power design techniques to offer both high speed and

low power. With an advanced E2 low power cell and non sense-amplifier design approach (full CMOS logic

approach), the ispMACH 4000 family offers SuperFAST pin-to-pin speeds, while simultaneously delivering low

standby power without needing any “turbo bits” or other power management schemes associated with a traditional

sense-amplifier approach.

The zero power ispMACH 4000Z is based on the 1.8V ispMACH 4000C family. With innovative circuit design

changes, the ispMACH 4000Z family is able to achieve the industry’s “lowest static power”.

IEEE 1149.1-Compliant Boundary Scan Testability

All ispMACH 4000 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows

functional testing of the circuit board on which the device is mounted through a serial scan path that can access all

critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto

test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked

into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS

interface that corresponds to the power supply voltage.

I/O Quick Configuration

To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu-

ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’

physical nature should be minimal so that board test time is minimized. The ispMACH 4000 family of devices allows

this by offering the user the ability to quickly configure the physical nature of the I/O cells. This quick configuration

takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's ispVM®

System programming software can either perform the quick configuration through the PC parallel port, or can gen-

erate the ATE or test vectors necessary for a third-party test system.

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