LH5116S 데이터 시트보기 (PDF) - Sharp Electronics
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LH5116S Datasheet PDF : 7 Pages
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LH5116S
CMOS 16K (2K × 8) Static RAM
(2) WRITE CYCLE (VCC = 3 V ±10%, TA = 0 to +50°C)
PARAMETER
SYMBOL
MIN.
TYP.
Write cycle time
tWC
1000
Chip enable to end of write
tCW
100
Address valid time
tAW
100
Address setup time
tAS
0
Write pulse width
tWP
100
Write recovery time
tWR
20
WE Low to output in High-Z
tWHZ
Data valid to end of write
tDW
50
Data hold time
tDH
20
Output active from end of write
tOW
10
Output enable to output in High-Z
tOHZ
0
NOTE:
1. Active output to high-impedance and high-impedance to output
active tests specified for a ±200 mV transition
from steady state levels into the test load.
MAX.
30
40
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE
1
1
1
AC TEST CONDITIONS
PARAMETER
MODE
Input voltage amplitude
Input rise/fall time
0 to VCC
10 ns
Timing reference level
1.5 V
Output load conditions
CL (100 pF)
NOTE:
1. Includes scope and jig capacitance.
NOTE
1
DATA RETENTION CHARACTERISTICS (TA = 0 to +50°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
Data retention voltage
VCCDR
CE ≥ VCCDR - 0.2 V
2.0
Data retention current
ICCDR
CE ≥ VCCDR - 0.2 V,
VCCDR = 2.0 V
1.0
0.2
Chip disable to data retention
tCDR
0
Recovery time
tR
tRC
NOTES:
1. TA = 25°C
2. tRC = Read cycle time
CAPACITANCE 1 (TA = 25°C, f = 1MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
Input capacitance
CIN
VIN = 0 V
7
Input/output capacitance
CI/O
VI/O = 0 V
10
NOTE:
1. This parameter is sampled and not production tested.
UNIT
V
µA
ns
ns
UNIT
pF
pF
NOTE
1
2
4
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