LH5PV8512N-12 데이터 시트보기 (PDF) - Sharp Electronics
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LH5PV8512N-12 Datasheet PDF : 12 Pages
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LH5PV8512
CMOS 4M (512K × 8) Pseudo-Static RAM
NOTES:
1. AC characteristics are measured at tT = 2 ns.
2. AC characteristics are measured at the following condition:
Input level
Input reference level
Output reference level
INPUT VOLTAGE
VIH
VIL
2.4 V
0.4 V
1.4 V
1.4 V
OUTPUT VOLTAGE
VOH
VOL
2.0 V
0.8 V
3. In order to initialize the circuit, CE and OE/RFSH should be kept VIH for 100 µs after power-up and followed by at least 8 dummy cycles.
4. If input signals of opposite phase to the outputs are applied in write cycle, OE or WE must disable output buffer proir to applying data to
the device and data inputs must be floating prior to OE or WE turning on outputs buffer.
5. Because a PSRAM operates dynamically like a DRAM, it is recommended to put bypass capacitors between VCC and GND to absorb power
supply noise due to the peak current.
6. Address signals are latched in the memory at the falling edge of CE.
7. Measured with a load equivalent to 50 pF.
8. tCLZ, tOLZ, tWLZ, tCHZ, tOHZ, and tWHZ are sampled, and not 100% tested. tCHZ, tOHZ, and tWHZ define the time at which the output achieves
the open circuit condition and they are not referenced to output voltage levels.
9. Input data is latched in the memory at the earlier rising edge of CE and WE.
10. CE only refresh or auto-refresh is needed to be executed 2,048 times within 32 ms.
11. Auto-refresh and self-refresh are defined by OE/RFSH pulse width during CE = VIH. If OE/RFSH pulse width is shorter than tFAP (MAX.),
the cycle is an auto-refresh cycle and memory cells are refreshed by an internal address counter. If OE/RFSH pulse width is longer than
tFAS (MIN.), the cycle is a self-refresh cycle and memory cells are refreshed by an internal clock generator automatically.
12. If CE only refresh is used during normal read/write cycles, the first address refresh must be started within 15 µs after self-refresh or data
retention mode ends, and the CE only refresh must be executed continuously for 2,048 refresh cycles.
13. If distributed auto-refresh is used during normal read/write cycles, the first auto-refresh must be started within 15 µs after self-refresh or
data retention mode ends.
14. If burst auto-refresh is used during normal read/write cycles, the first auto-refresh must be started within 15 µs after self-refresh or data
retention mode ends, and the auto-refresh must be executed continuously for 2,048 refresh cycles.
15. After 8,000 ns (tFAP (MAX.)) from RFSH falling, the memory resets its internal address counter and enters self-refresh cycle. At the beginning
of the self-refresh cycle, it takes longer than 8 ms (tFAS (MIN.)) for all addresses to be refreshed. Therefore, in case that the RFSH = L
pulse length is from 8,000 ns to 8 ms, refresh all addresses by external clocks within 32 ms before the self-refresh to keep refresh time
interval (tREF).
16. After self-refresh cycle or data retention mode ends, tFRS (MIN.) is necessary to reset the refresh operation. CE and OE/RFSH should kept
VIH for tFRS (MIN.).
17. The data retention period is longer than tFAS (MIN.) like self-refresh cycle.
18. OE/RFSH must be lower than 0.2 V during the data retention period.
19. CE must be higher than VCC - 0.2 V during the data retention period.
20. The transition time of the supply voltage in data retention mode must be slower than 0.05 V/ms.
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