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LPC2106BBD48 데이터 시트보기 (PDF) - Philips Electronics

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LPC2106BBD48 Datasheet PDF : 32 Pages
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Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.10 UARTs
The LPC2104, LPC2105 and LPC2106 each contain two UARTs. One UART
provides a full modem control handshake interface, the other provides only transmit
and receive data lines.
6.10.1 Features
16 byte Receive and Transmit FIFOs.
Register locations conform to ‘550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
Built-in baud rate generator.
Standard modem interface signals included on UART 1.
6.11 I2C serial I/O controller
I2C is a bi-directional bus for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address
and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter
with the capability to both receive and send information (such as memory).
Transmitters and/or receivers can operate in either master or slave mode, depending
on whether the chip has to initiate a data transfer or is only addressed. I2C is a
multi-master bus, it can be controlled by more than one bus master connected to it.
I2C implemented in LPC2104, LPC2105 and LPC2106 supports bit rate up to
400 kbit/s (Fast I2C).
6.11.1 Features
Standard I2C compliant bus interface.
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer.
The I2C bus may be used for test and diagnostic purposes.
9397 750 12792
Product data
Rev. 04 — 05 February 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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