LT3579IUFD-1-PBF(RevA) 데이터 시트보기 (PDF) - Linear Technology

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LT3579IUFD-1-PBF
(Rev.:RevA)

6A Boost/Inverting DC/DC Converter with Fault Protection

Linear Technology 

LT3579/LT3579-1

APPLICATIONS INFORMATION

where fOSC is in MHz and RT is in kΩ. Conversely, RT (in

kΩ) can be calculated from the desired frequency (in

MHz) using:

RT

=

87.6

fOSC

–1

Clock Synchronization

An external source can set the operating frequency of the

LT3579 by providing a digital clock signal into the SYNC

pin (RT resistor still required). The LT3579 will operate at

the SYNC clock frequency. The LT3579 will revert to its

internal free-running oscillator clock when the SYNC pin is

driven below 0.4V for a few free-running clock periods.

Driving SYNC high for an extended period of time

effectively stops the operating clock and prevents latch

SR1 from becoming set (see Block Diagram). As a result,

the switching operation of the LT3579 will stop and the

CLKOUT pin will be held at ground.

The duty cycle of the SYNC signal must be between 20%

and 80% for proper operation. Also, the frequency of the

SYNC signal must meet the following two criteria:

1. SYNC may not toggle outside the frequency

range of 200kHz-2.5MHz unless it is stopped

below 0.4V to enable the free-running oscillator.

2. The SYNC frequency can always be higher than

the free-running oscillator frequency (as set by the

RT resistor), fOSC, but should not be less than 25%

below fOSC.

CLOCK SYNCHRONIZATION OF ADDITIONAL

REGULATORS

The CLKOUT pin of the LT3579 can synchronize additional

switching regulators and/or additional LT3579s as shown

in Figure 12.

3.3µH

10µF

SW1 SW2

GATE

CLKOUT

4.7µF

VIN LT3579

SLAVE

FAULT

SHDN

RT SYNC

FB

VC

SS

GND

86.6k

200k

68pF

8k

0.1µF

3.3nF

VOUT

18V

1A

10µF

×2

VIN

5V

10k

4.7µF

10µF

100k

110k

2.2µH

SW1 SW2

GATE

CLKOUT

VIN LT3579 FB

MASTER

FAULT

VC

SHDN

SS

RT SYNC GND

86.6k

130k

47pF

0.1µF

8k

2.2nF

VOUT

12V

1.7A

10µF

×3

35791 F12

Figure 12. Synchronize Multiple LT3579s. The External PMOS

Disconnects the Input from Both Power Paths During FAULT Events

For more information www.linear.com/LT3579

35791fa

21

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