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LT3580I 데이터 시트보기 (PDF) - Linear Technology

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LT3580I Datasheet PDF : 28 Pages
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APPLICATIONS INFORMATION
LT3580
1
C1
2
VIN
3
L1
4
SW
D1 C2
VOUT
GND
8
9
7
6
5
SYNC
SHDN
3580 F09
VIAS TO GROUND
PLANE REQUIRED
TO IMPROVE
THERMAL
PERFORMANCE
Figure 9. Suggested Component Placement for Boost Topology
(Both DFN and MSOP Packages. Not to Scale). Pin 9 (Exposed
Pad) Must Be Soldered Directly to the Local Ground Plane for
Adequate Thermal Performance. Multiple Vias to Additional
Ground Planes Will Improve Thermal Performance
GND
C1
VIN
L1
SW
1
8
2
9
7
3
6
4
5
SYNC
SHDN
L2
C2
D1 C3
VOUT
3580 F10
VIAS TO GROUND
PLANE REQUIRED
TO IMPROVE
THERMAL
PERFORMANCE
Figure 10. Suggested Component Placement for Sepic Topology
(Both DFN And MSOP Packages. Not to Scale). Pin 9 (Exposed
Pad) Must Be Soldered Directly to the Local Ground Plane for
Adequate Thermal Performance. Multiple Vias to Additional
Ground Planes Will Improve Thermal Performance
GND
1
C1
2
VIN
3
4
L1
SW
L2
C2
D1
C3
VOUT
8
9
7
6
5
SYNC
SHDN
3580 F11
VIAS TO GROUND
PLANE REQUIRED
TO IMPROVE
THERMAL
PERFORMANCE
Figure 11. Suggested Component Placement for Inverting Topology (Both DFN and MSOP Packages. Not to Scale).
Note Cut in Ground Copper at Diode’s Cathode. Pin 9 (Exposed Pad) Must be Soldered Directly to Local Ground
Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal
Performance
3580fg
17

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