LTC2938 데이터 시트보기 (PDF) - Linear Technology
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LTC2938 Datasheet PDF : 20 Pages
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LTC2938/LTC2939
APPLICATIONS INFORMATION
After RST returns high, the microprocessor can poll the
state of the WDO pin to determine if the reset was caused
by an undervoltage condition or by a watchdog timeout.
WDO high means that the reset was caused by undervolt-
age since this condition also resets the WDO latch (and
the watchdog timer). If the WDO pin is low, the system
reset was caused by watchdog timeout. The microproces-
sor can then change the state of WDI to clear the WDO
latch. If the microprocessor fails to do so, the LTC2938/
LTC2939 will alternate between tRST and tWD timeout
and RST will be pulled low for tRST after every watchdog
timeout. WDO remains low until the microprocessor flips
the state of WDI.
Some microprocessors force their I/O pins into high
impedance during reset which in turn, floats the WDI
pin. This affects the response of the LTC2938/LTC2939.
When the WDI pin is floated, the watchdog timer is reset
and CWT is discharged towards ground but WDO remains
unchanged. Putting WDI in high impedance does not affect
tRST. Once RST goes high again, and WDI is driven from
high impedence to a high or low state, the watchdog timer
starts a complete tWD timeout period. A high-to-low or
low-to-high transition at WDI clears WDO if it was previ-
ously latched low.
The RST and WDO pins should not be tied together to
generate the master reset signal since a watchdog timeout
forces RST low together with WDO and the master reset
signal will remain low indefinitely.
5V
3.3V
0.1μF
2.5V
1.8V
12V
2150k 1%
1.2V 124k 1%
100k 100k
1%
1%
V1
V2
0.1μF
R1
59k
1%
R2
40.2k
1%
V3
LTC2939
V4
V5
V6
VREF
RST
WDO
WDI
MICROPROCESSOR
VPG GND CRT
CWT
CRT
47nF
CWT
47nF
293839 F05
tRST = 94ms
tWD = 940ms
Figure 5. 6-Supply Monitor, 12V (ADJ), 5V, 3.3V, 2.5V, 1.8V, 1.2V (ADJ)
with Watchdog Enabled
14
293839ff
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