LTC6801HG-PBF 데이터 시트보기 (PDF) - Linear Technology

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LTC6801HG-PBF

Independent Multicell Battery Stack Fault Monitor

Linear Technology 

LTC6801

APPLICATIONS INFORMATION

For a given sample rate, a delta-sigma converter can

achieve excellent noise rejection while settling completely

in a single conversion. This is particularly important for

noisy automotive systems. Other advantages of delta-sigma

converters are that they are inherently monotonic, mean-

ing they have no missing codes, and they have excellent

DC specifications.

The LTC6801’s ADC has a second order delta-sigma

modulator followed by a SINC2, finite impulse response

(FIR) digital filter, with a lowpass bandwidth of 1kHz. The

front-end sample rate is 512ksps, which greatly reduces

input filtering requirements. A simple 16kHz, 1 pole filter

composed of a 1k resistor and a 10nF capacitor at each

input will provide adequate filtering for most applications.

These component values will not degrade the DC accuracy

of the ADC.

Each conversion consists of two phases – an autozero

phase and a measurement phase. The ADC is autozeroed

at each conversion, greatly improving CMRR.

USING TRANSFORMERS FOR GALVANIC ISOLATION

As shown in Figure 12, small gate-drive signal transform-

ers can be used to interconnect devices and transport the

enable and sense signals safely across an isolation barrier.

Driving a transformer with a squarewave requires transient

currents of several mA and frequency of operation at 20kHz

or higher. Since the output pins of the LTC6801 are current

limited at <1mA, a small external gate pair (NC7WZ17 dual

buffer) is used to provide the needed drive current. 330Ω

resistors are placed in series with each buffer output to

optimize current flow into the transformer primary and a

coupling capacitor provides prevention of current flow in

static conditions. The secondary side is wired in a cen-

ter-tapped configuration to terminate the common mode

voltage and thus suppress noise pickup. The differential

signal is terminated into 1500Ω to optimize the peak signal

swing for the IC input (to about ±4VP-P). Internal biasing

features of the IC inputs maintain an optimal DC common

mode level at the transformer secondary.

22

INTERCOMMUNICATION USING DATA ISOLATORS

As shown in Figure 13, an inexpensive and compact

2-channel data isolator is used to communicate the enable

and the sense clocking signals between devices. The wiring

carries isolator power and return plus two single-ended

logic signals that are completely isolated at the upper device

interface, so the signals are effectively differential from a

common mode ingress perspective. The isolator provides

excellent rejection of noise between battery groups, but

consumes a few mA when operating, so a conventional

opto-coupler and a few discretes provide a power-down

scheme for periods where no monitoring is needed. Since

the required current would load down VREG if used directly,

the NPN transistor is used to form a quasi-regulated 4.3V

supply drawing from the full battery group potential, also

moving significant thermal loading outside the IC. The

PMOS FET is a low resistance switch controlled by the

opto-coupler output. Since the opto-coupler is used to

switch only a small current, the LED need only be driven

with ~500μA. Powering down the bottom-of-stack isolator

on the host μP side automatically powers down the entire

isolator chain.

DEMO BOARD CIRCUIT

An LTC6801 demonstration circuit is shown in Figure 14.

The circuit includes a 10kHz oscillator (U2) for the enable

excitation and an LED (D15, driven by Q1) to indicate the

state of the status outputs, plus an assortment of important

protection components to ensure robust operation and

hot-plugging of cell connections.

Series resistors (R14 to R21) provide a controlled coupling

capacitor (C14 to C17) current in the inter-IC connections

during startup or other abrupt potential changes, and as-

sociated clamp diodes (D13 and D14 quad array devices)

redirect charge/surge current around the IC.

Input filters to each cell (R1, C1 to R12, C12) also use

6.2V Zener diodes (D1 to D12) to prevent overstress to

the internal ESD clamps.

The V+ input filter (R13, C13) has the same time constant

as the ADC input filters so that the V+ and C12 pins tend

to track during start-up or transients, minimizing stress

and ADC error.

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