LTM4618(RevA) 데이터 시트보기 (PDF) - Linear Technology

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LTM4618
(Rev.:RevA)

6A DC/DC µModule Regulator with Tracking and Frequency Synchronization

Linear Technology 

LTM4618

APPLICATIONS INFORMATION

board, and is really the sum of the θJCbottom and the

thermal resistance of the bottom of the part through

the solder joints and through a portion of the board.

The board temperature is measured at specified dis-

tance from the package, using a two sided, two layer

board. This board is described in JESD 51-9.

A graphical representation of the forementioned thermal

resistances is given in Figure 6; blue resistances are

contained within the μModule regulator, whereas green

resistances are external to the μModule regulator.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD 51-12 or provided in the

Pin Configuration section replicates or conveys normal

operating conditions of a μModule regulator. For example,

in actual board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bot-

tom of the μModule regulator—as the standard defines

for θJCtop and θJCbottom, respectively. In practice, power

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within a SIP (System-In-Package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the μModule regulator and the specified PCB

with all of the correct material coefficients along with

accurate power loss source definitions; (2) this model

simulates a software-defined JEDEC environment consis-

tent with JSED51-9 to predict power loss heat flow and

temperature readings at different interfaces that enable

the calculation of the JEDEC-defined thermal resistance

values; (3) the model and FEA software is used to evalu-

ate the μModule regulator with heat sinks and airflow; (4)

having solved for and analyzed these thermal resistance

values and simulated various operating conditions in the

software model, a thorough laboratory evaluation replicates

the simulated conditions with thermocouples within a

controlled-environment chamber while operating the device

at the same power loss as that which was simulated. An

outcome of this process and due-diligence yields a set

of derating curves provided in other sections of this data

sheet. After these laboratory tests have been performed

and correlated to the μModule package model, then the

θJB and θBA are summed together to correlate quite well

with the μModule package model with no air flow or heat

sinking in a properly define chamber. This θJB+ θBA value

is shown in the Pin Configuration section and should ac-

curately equal the θJA value because approximately 100%

of power loss flows from the junction through the board

into ambient with no airflow or top mounted heat sink.

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

JUNCTION-TO-CASE (TOP)

RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION

At

JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD

(BOTTOM) RESISTANCE

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

μMODULE DEVICE

4618 F06

Figure 6. Graphical Representation of JESD51-12 Thermal Coefficients

4618fa

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