M24C64-DFBN6G 데이터 시트보기 (PDF) - STMicroelectronics

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M24C64-DFBN6G

64-Kbit serial I²C bus EEPROM

STMicroelectronics 

Instructions

M24C64-W M24C64-R M24C64-F

5.1.6

Minimizing Write delays by polling on ACK

During the internal Write cycle, the device disconnects itself from the bus, and writes a copy

of the data from its internal latches to the memory cells. The maximum Write time (tw) is

shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time

is shorter. To make use of this, a polling sequence can be used by the bus master.

The sequence, as shown in Figure 11, is:

• Initial condition: a Write cycle is in progress.

• Step 1: the bus master issues a Start condition followed by a device select code (the

first byte of the new instruction).

• Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and

the bus master goes back to Step 1. If the device has terminated the internal Write

cycle, it responds with an Ack, indicating that the device is ready to receive the second

part of the instruction (the first byte of this instruction having been sent during Step 1).

Figure 11. Write cycle polling flowchart using ACK

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1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the

figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling

instruction in the figure).

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