M24M01-RMN3G/A 데이터 시트보기 (PDF) - STMicroelectronics
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M24M01-RMN3G/A Datasheet PDF : 37 Pages
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Device operation
M24M01-R, M24M01-W, M24M01-HR
3.10
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Table 13, but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.
The sequence, as shown in Figure 10, is:
● Initial condition: a Write cycle is in progress.
● Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
● Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 11. Read mode sequences
Current
Address
Read
ACK
NO ACK
Dev sel
Data out
R/W
Random
Address
Read
ACK
ACK
ACK
ACK
NO ACK
Dev sel *
Byte addr
Byte addr
Dev sel *
Data out
R/W
R/W
Sequential
Current
Read
ACK
ACK
Dev sel
Data out 1
R/W
ACK
NO ACK
Data out N
Sequention
Random
Read
ACK
ACK
ACK
ACK
ACK
Dev sel *
Byte addr
Byte addr
Dev sel *
Data out1
R/W
R/W
ACK
NO ACK
Data out N
AI01105d
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must
be identical.
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Doc ID 12943 Rev 7
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