M25P40-VMN6TP/4A 데이터 시트보기 (PDF) - Numonyx -> Micron

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M25P40-VMN6TP/4A

4 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface

Numonyx -> Micron 

M25P40

Instructions

Table 4. Instruction set

Instruction

Description

One-byte instruction Address Dummy Data

code

bytes bytes bytes

WREN Write Enable

0000 0110 06h

0

0

0

WRDI

RDID(1)

RDSR

Write Disable

Read Identification

Read Status Register

0000 0100 04h

0

1001 1111 9Fh

0

0000 0101 05h

0

0

0

0

1 to 3

0

1 to ∞

WRSR

READ

Write Status Register

Read Data Bytes

0000 0001 01h

0

0000 0011 03h

3

0

1

0

1 to ∞

Read Data Bytes at Higher

FAST_READ

0000 1011 0Bh

3

Speed

1

1 to ∞

PP

Page Program

0000 0010 02h

3

0 1 to 256

SE

Sector Erase

1101 1000 D8h

3

0

0

BE

Bulk Erase

1100 0111 C7h

0

0

0

DP

Deep Power-down

1011 1001 B9h

0

0

0

Release from Deep Power-

down, and Read Electronic

0

RES

Signature

1010 1011 ABh

Release from Deep Power-

0

down

3

1 to ∞

0

0

1. The Read Identification (RDID) instruction is available only in products with Process Technology code X

and 4 (see Application Note AN1995).

6.1

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector

Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.

The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

Figure 7. Write Enable (WREN) instruction sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI02281E

19/57

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