Clock operation
M41T56
Figure 12. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
–120
–140
–160
–40 –30 –20 –10 0
∆F
F
=
K
x
(T
–TO)2
K = –0.036 ppm/°C2 ± 0.006 ppm/°C2
TO = 25°C ± 5°C
10 20 30 40 50 60 70 80
Temperature °C
AI00999b
Figure 13. Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
3.2
Note:
3.3
Output driver pin
When the FT Bit is not set, the FT/OUT pin becomes an output driver that reflects the
contents of D7 of the Control Register. In other words, when D6 of location 7 is a '0' and D7
of location 7 is a '0' and then the FT/OUT pin will be driven low.
The FT/OUT pin is open drain which requires an external pull-up resistor.
Initial power-on defaults
Upon initial application of power to the device, the FT Bit will be set to a '0' and the OUT Bit
will be set to a '1.' All other Register bits will initially power-on in a random state.
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