X28LC512 데이터 시트보기 (PDF) - Xicor -> Intersil

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X28LC512

3.3 Volt, Byte Alterable E2PROM

Xicor -> Intersil 

X28LC512/X28LC513

DATA Polling Timing Diagram(7)

ADDRESS

An

An

CE

WE

tOEH

OE

I/O7

DIN=X

DOUT=X

tWC

An

tOES

tDW

DOUT=X

3005 ILL F09

Toggle Bit Timing Diagram

CE

WE

tOEH

OE

I/O6

HIGH Z

*

tWC

tOES

tDW

*

* Starting and ending state of I/O6 will vary, depending upon actual tWC.

3005 ILL F10

Note: (7) Polling operations are by definition read cycles and are therefore subject to read cycle timings.

15

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