M2V56S20TP-6 데이터 시트보기 (PDF) - Mitsumi

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M2V56S20TP-6

256M Synchronous DRAM

Mitsumi 

SDRAM (Rev.1.1)

Single Data Rate

Feb.2000

MITSUBISHI LSIs

M2V56S20/ 30/ 40/ TP -6, -7, -8

256M Synchronous DRAM

POWER ON SEQUENCE

Before starting normal operation, the following power on sequence is necessary to prevent a

SDRAM from damaged or malfunctioning.

1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.

2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.

3. Issue precharge commands for all banks. (PRE or PREA)

4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

After these sequence, the SDRAM is idle state and ready for normal operation.

MODE REGISTER

CLK

Burst Length, Burst Type and /CAS Latency can be programmed by

setting the mode register (MRS). The mode register stores these data

/CS

until the next MRS command, which may be issued when all banks are /RAS

in idle state. After tRSC from a MRS command, the SDRAM is ready

/CAS

for new command.

/WE

BA0,1 A12-A0

V

BA0 BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 SW 0 0 LTMODE BT

BL

0 Burst Write

SW 1 Single Write

LATENCY

MODE

CL

000

001

010

011

100

101

110

111

/CAS LATENCY

R

R

2

3

R

R

R

R

R: Reserved for Future Use

BURST

LENGTH

BL

000

001

010

011

100

101

110

111

BT=0

1

2

4

8

R

R

R

Full Page

BT=1

1

2

4

8

R

R

R

R

BURST

0

TYPE

1

SEQUENTIAL

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MITSUBISHI ELECTRIC

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