M58BW016DB80T3(2003) 데이터 시트보기 (PDF) - STMicroelectronics

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M58BW016DB80T3
(Rev.:2003)

16 Mbit (512Kb x32, Boot Block, Burst) 3V Supply Flash Memories

STMicroelectronics 

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

the Address Inputs and pulsing Latch Enable Low,

VIL. The Address Inputs are latched by the Com-

mand Interface on the rising edge of Latch Enable,

Write Enable or Chip Enable, whichever occurs

first. Commands and Input Data are latched on the

rising edge of Chip Enable, E, or Write Enable, W,

whichever occurs first. Output Enable must remain

High, and Output Disable Low, during the whole

Asynchronous Bus Write operation.

See Figure 13, Asynchronous Latch Controlled

Write AC Waveforms, and Table 19, Asynchro-

nous Write and Latch Controlled Write AC Charac-

teristics, for details of the timing requirements.

Output Disable. The data outputs are high im-

pedance when the Output Enable, G, is at VIH or

Output Disable, GD, is at VIL.

Standby. When Chip Enable is High, VIH, and the

Program/Erase Controller is idle, the memory en-

ters Standby mode, the power consumption is re-

duced to the standby level and the Data Inputs/

Outputs pins are placed in the high impedance

state regardless of Output Enable, Write Enable or

Output Disable inputs.

Automatic Low Power. If there is no change in

the state of the bus for a short period of time during

Asynchronous Bus Read operations the memory

enters Auto Low Power mode where the internal

Supply Current is reduced to the Auto-Standby

Supply Current. The Data Inputs/Outputs will still

output data if a Bus Read operation is in progress.

Automatic Low Power is only available in Asyn-

chronous Read modes.

Power-Down. The memory is in Power-down

when Reset/Power-Down, RP, is at VIL. The pow-

er consumption is reduced to the power-down lev-

el and the outputs are high impedance,

independent of the Chip Enable, E, Output Enable,

G, Output Disable, GD, or Write Enable, W, inputs.

Electronic Signature. Two codes identifying the

manufacturer and the device can be read from the

memory allowing programming equipment or ap-

plications to automatically match their interface to

the characteristics of the memory. The Electronic

Signature is output by giving the Read Electronic

Signature command. The manufacturer code is

output when all the Address inputs are at VIL. The

device code is output when A1 is at VIH and all the

other address pins are at VIL. See Table 5. Issue

a Read Memory Array command to return to Read

mode.

Table 4. Asynchronous Bus Operations

Bus Operation

Step

E G GD W RP L

Asynchronous Bus Read

VIL VIL VIH VIH VIH VIL

Asynchronous Latch

Controlled Bus Read

Address Latch VIL VIH VIH VIL VIH VIL

Read

VIL VIL VIH VIH VIH VIH

Asynchronous Page

Read

VIL VIL VIH VIH VIH

X

Asynchronous Bus Write

VIL VIH

X

VIL VIH VIL

Asynchronous Latch

Controlled Bus Write

Address Latch VIL VIL VIH VIH VIH VIL

Write

VIL VIH

X

VIL VIH VIH

Output Disable, G

VIL VIH VIH VIH VIH

X

Output Disable, GD

VIL VIL VIL VIH VIH

X

Standby

VIH X

X

X VIH X

Reset/Power-Down

Note: X = Don’t Care

X

X

X

X

VIL

X

A0-A18

Address

Address

X

Address

Address

Address

X

X

X

X

X

DQ0-DQ31

Data Output

High Z

Data Output

Data Output

Data Input

High Z

Data Input

High Z

High Z

High Z

High Z

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