M58BW016DB(2003) 데이터 시트보기 (PDF) - STMicroelectronics
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M58BW016DB
(Rev.:2003)
(Rev.:2003)
STMicroelectronics
M58BW016DB Datasheet PDF : 63 Pages
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M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
Table 7. Burst Configuration Register
Bit
Description
Value
Description
M15
Read Select
0
Synchronous Burst Read
1
Asynchronous Read (Default at power-on)
M14
Reserved
001
Reserved
010
4, 4-1-1-1 (1)
M13-M11
X-Latency (2)
011
5, 5-1-1-1, 5-2-2-2
100
6, 6-1-1-1, 6-2-2-2
101
7, 7-1-1-1, 7-2-2-2
110
8, 8-1-1-1, 8-2-2-2
M10
Reserved
M9
Y-Latency (3)
0
One Burst Clock cycle
1
Two Burst Clock cycles
0
M8
Valid Data Ready
1
R valid Low during valid Burst Clock edge
R valid Low one data cycle before valid Burst Clock edge
M7
Burst Type
0
Interleaved
1
Sequential
0
M6
Valid Clock Edge
1
Falling Burst Clock edge
Rising Burst Clock edge
M5-M4
Reserved
M3
Wrapping
0
Wrap
1
No wrap
001
4 Double-Words
M2-M0
Burst Length
010
8 Double-Words
111
Continuous
Note: 1. 4 - 2 - 2 - 2 is not allowed.
2. X latencies can be calculated as: (tAVQV – tLLKH + tQVKH) + tSYSTEM MARGIN < (X -1) tK. (X is an integer number from 4 to 8 and tK
is the clock period).
3. Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tQVKH < Y tK.
4. tSYSTEM MARGIN is the time margin required for the calculation.
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