LC75863E 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC75863E

1/3 Duty LCD Display Drivers with Key Input Function

SANYO -> Panasonic 

LC75863E, 75863W

2. LC75863E/W internal block states during the reset period

• CLOCK GENERATOR

Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined

after the S0 and S1 control data bits are transferred.

• COMMON DRIVER, SEGMENT DRIVER & LATCH

Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.

• KEY SCAN

Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.

• KEY BUFFER

Reset is applied and all the key data is set to low.

• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER

Since serial data transfer is possible, these circuits are not reset.

VLCD

VLCD1

VLCD2

VSS

TEST

OSC

DO

DI

CL

CE

VDD

COMMON

DRIVER

CLOCK

GENERATOR

CCB

INTERFACE

VDET

SEGMENT DRIVER & LATCH

SHIFT REGISTER

CONTROL

REGISTER

KEY BUFFER

KEY SCAN

Blocks that are reset

No. 7135-17/24

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