MC80C86 데이터 시트보기 (PDF) - Intel
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MC80C86 Datasheet PDF : 19 Pages
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M80C86 M80C86-2
A C CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol
Parameter
M80C86
Min Max
M80C86-2
Units
Min Max
Comments
TCLML Command Active
Delay (Note 1)
5
45
5
35 ns
TCLMH Command Inactive
Delay (Note 1)
5
45
5
35 ns
TRYHSH READY Active to
Status Passive (Note 3)
110
65 ns
TCHSV Status Active Delay
10
110
10
60 ns
TCLSH Status Inactive Delay
10
130
10
70 ns
TCLAV Address Valid Delay
10
110
10
60 ns
TCLAX Address Hold Time
10
10
ns
TCLAZ Address Float Delay
TCLAX 80 TCLAX 50 ns
TSVLH Status Valid to ALE High (Note 1)
35
20 ns
TSVMCH Status Valid to
MCE High (Note 1)
35
30 ns
TCLLH CLK Low to ALE Valid (Note 1)
35
20 ns
TCLMCH CLK Low to MCE High (Note 1)
35
25 ns
TCHLL ALE Inactive Delay (Note 1)
4
35
4
25 ns
TCLDV Data Valid Delay
10
110
10
60 ns
TCHDX Data Hold Time
10
10
ns
TCVNV Control Active Delay (Note 1)
5
45
5
45 ns
TCVNX Control Inactive Delay (Note 1)
5
45
10
45 ns
TAZRL Address Float to Read Active
0
0
ns
TCLRL RD Active Delay
10
165
10
100 ns
TCLRH RD Inactive Delay
10
150
10
80 ns
TRHAV RD Inactive to
Next Address Active
TCLCLb45
TCLCLb40
ns
TCHDTL Direction Control
Active Delay (Note 1)
50
50 ns
TCHDTH Direction Control
Inactive Delay (Note 1)
35
30 ns
TCLGL GT Active Delay
0
85
0
50 ns
TCLGH GT Inactive Delay
0
85
0
50 ns
TRLRH RD Width
2TCLCLb75
2TCLCLb50
ns
TOLOH Output Rise Time
15
15 ns From 0 8V to 2 0V
TOHOL Output Fall Time
15
15 ns From 2 0V to 0 8V
NOTES
1 Signal at M82C84A or M82C88 shown for reference only See M82C84A and M82C88 for the most recent specifications
2 Setup requirement for asynchronous signal only to guarantee recognition at next CLK
3 Applies only to T3 and wait states
4 Applies only to T2 state (5 ns into T3)
15
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