M80C186XL10 데이터 시트보기 (PDF) - Intel
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M80C186XL10 Datasheet PDF : 44 Pages
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M80C186XL
AC CHARACTERISTICS
MAJOR CYCLE TIMINGS (READ CYCLE)
TC e b55 C to a125 C VCC e 5V g10%
All timings are measured at 1 5V and 100 pF loading on CLKOUT unless otherwise noted
All output test conditions are with CL e 50 pF
For AC tests input VIL e 0 45V and VIH e 2 4V except at X1 where VIH e VCC b 0 5V
Values
Symbol
Parameter
M80C186XL
M80C186XL12 Unit
Min
Max
Min
Max
M80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)
TDVCL Data in Setup (A D)
15
15
ns
TCLDX Data in Hold (A D)
3
3
ns
M80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)
TCHSV
TCLSH
TCLAV
TCLAX
TCLDV
TCHDX
TCHLH
TLHLL
TCHLL
TAVLL
Status Active Delay
Status Inactive Delay
Address Valid Delay
Address Hold
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
ALE Inactive Delay
Address Valid to ALE Low
3
45
3
35 ns
3
46
3
35 ns
3
44
3
36 ns
0
0
ns
3
40
3
36 ns
10
10
ns
30
25 ns
TCLCL b 15
TCLCL b 15
ns
30
25 ns
TCLCH b 18
TCLCH b 15
ns
TLLAX Address Hold from ALE
TCHCL b 15
TCHCL b 15
ns
Inactive
TAVCH Address Valid to Clock High
0
0
ns
TCLAZ Address Float Delay
TCLAX
30
TCLAX
25 ns
TCLCSV Chip-Select Active Delay
3
42
3
33 ns
TCXCSX Chip-Select Hold from
TCLCH b 10
TCLCH b 10
ns
Command Inactive
TCHCSX Chip-Select Inactive Delay
3
35
3
30 ns
TDXDL DEN Inactive to DT R Low
0
0
ns
TCVCTV Control Active Delay 1
3
44
3
37 ns
TCVDEX DEN Inactive Delay
3
44
3
37 ns
TCHCTV Control Active Delay 2
3
44
3
37 ns
TCLLV LOCK Valid Invalid Delay
3
40
3
37 ns
M80C186XL TIMING RESPONSES (Read Cycle)
TAZRL Address Float to RD Active
0
0
ns
TCLRL RD Active Delay
3
44
3
37 ns
TRLRH RD Pulse Width
2TCLCL b 30
2TCLCL b 25
ns
TCLRH RD Inactive Delay
3
44
3
37 ns
TRHLH RD Inactive to ALE High
TCLCH b 14
TCLCH b 14
ns
TRHAV RD Inactive to Address
TCLCL b 15
TCLCL b 15
ns
Active
Test
Conditions
Equal
Loading
Equal
Loading
Equal
Loading
Equal
Loading
Equal
Loading
Equal
Loading
16
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