M95040-SBN3T 데이터 시트보기 (PDF) - STMicroelectronics

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M95040-SBN3T

4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

M95040, M95020, M95010

SIGNAL DESCRIPTION

VCC must be held within the specified range:

VCC(min) to VCC(max).

All of the input and output signals can be held High

or Low (according to voltages of VIH, VOH, VIL or

VOL, as specified in Tables 12 to 16). These sig-

nals are described next.

Serial Data Output (Q)

This output signal is used to transfer data serially

out of the device. Data bytes are shifted out on the

falling edge of the Serial Clock (C).

Serial Data Input (D)

This input signal is used to transfer data serially

into the device. Instructions, addresses, and input

data bytes are shifted in on the rising edge of the

Serial Clock (C).

Serial Clock (C)

This input signal provides the timing for the serial

interface.

Chip Select (S)

When this input signal is High, the device is dese-

lected, and the Serial Data Output (Q) is high im-

pedance.

Hold (HOLD)

This input signal is used to pause temporarily any

serial communications with the device, without los-

ing bits that have already been passed on the se-

rial bus.

Write Protect (W)

This input signal is used to control whether the

memory is write protected. When W is held Low,

writes to the memory are disabled, but other oper-

ations remain enabled. No action on this signal, or

on the Write Enable Latch (WEL) bit, can interrupt

a Write cycle that has already started.

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