M95160-RMC6(2014) 데이터 시트보기 (PDF) - STMicroelectronics

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M95160-RMC6
(Rev.:2014)

16-Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

Instructions

M95160 M95160-W M95160-R M95160-DF

Table 6. Protection modes

W SRWD

signal bit

Mode

Write protection of the

Status Register

Memory content

Protected area(1) Unprotected area(1)

1

0

Status Register is writable

0

1

0

1

Software-

protected

(SPM)

(if the WREN instruction

has set the WEL bit).

The values in the BP1

and BP0 bits can be

Write-protected

Ready to accept

Write instructions

changed.

Status Register is

0

1

Hardware-

protected

(HPM)

Hardware write-

protected.

The values in the BP1

and BP0 bits cannot be

Write-protected

Ready to accept

Write instructions

changed.

1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2.

The protection features of the device are summarized in Table 6.

When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register (provided that the WEL bit has

previously been set by a WREN instruction), regardless of the logic level applied on the

Write Protect (W) input pin.

When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two

cases should be considered, depending on the state of the Write Protect (W) input pin:

• If Write Protect (W) is driven high, it is possible to write to the Status Register (provided

that the WEL bit has previously been set by a WREN instruction).

• If Write Protect (W) is driven low, it is not possible to write to the Status Register even if

the WEL bit has previously been set by a WREN instruction. (Attempts to write to the

Status Register are rejected, and are not accepted for execution). As a consequence,

all the data bytes in the memory area, which are Software-protected (SPM) by the

Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected

against data modification.

Regardless of the order of the two events, the Hardware-protected mode (HPM) can be

entered by:

• either setting the SRWD bit after driving the Write Protect (W) input pin low,

• or driving the Write Protect (W) input pin low after setting the SRWD bit.

Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to

pull high the Write Protect (W) input pin.

If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode

(HPM) can never be activated, and only the Software-protected mode (SPM), using the

Block Protect (BP1, BP0) bits in the Status Register, can be used.

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