MAX1820 데이터 시트보기 (PDF) - Maxim Integrated

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MAX1820

WCDMA Cellular Phone 600mA Buck Regulators

Maxim Integrated 

WCDMA Cellular Phone 600mA

Buck Regulators

Applications Information

Setting the Output Voltage (MAX1820)

The MAX1820 is optimized for highest system efficiency

when applying power to a linear PA in WCDMA hand-

sets. When transmitting at less than full power, the sup-

ply voltage to the PA is reduced (from 3.4V to as low as

0.4V) to greatly reduce battery current. Figure 4 shows

the typical WCDMA PA load profile. The use of a DC-

DC converter such as the MAX1820 dramatically

reduces battery drain in these applications.

3.4

3.0

1.0

0.4

30

300

600

WCDMA PA SUPPLY CURRENT (mA)

Figure 4. Typical WCDMA PA Load Profile

The MAX1820’s output voltage is dynamically

adjustable from 0.4V to VBATT by the use of the REF

input. The gain from VREF to VOUT is internally set to

1.76. VOUT can be adjusted during operation by driving

REF with an external DAC. The MAX1820 output

responds to full-scale change in voltage and current in

<30µs.

Setting the Output Voltage (MAX1821)

The MAX1821 is intended for general-purpose step-

down applications where high efficiency is a priority.

Select an output voltage between 1.25V and VBATT by

connecting FB to a resistive divider between the output

and GND (Figure 3). Select feedback resistor R2 in the

5kΩ to 30kΩ range. R1 is then given by:

R1

=

R2

⎛

⎝⎜

VOUT

VFB

⎞

-1⎠⎟

where VFB = 1.25V.

Compensation and Stability

The MAX1820/MAX1821 are externally compensated

by placing a resistor and a capacitor (RC and C1) in

series, from COMP to GND (Figure 3). The capacitor

integrates the current from the transimpedance amplifi-

er, averaging output capacitor ripple. This sets the

device speed for transient responses and allows the

use of small ceramic output capacitors because the

phase-shifted capacitor ripple does not disturb the cur-

rent regulation loop. The resistor sets the proportional

gain of the output error voltage by a factor gm ✕ RC.

Increasing this resistor also increases the sensitivity of

the control loop to the output capacitor ripple.

This resistor and capacitor set a compensation zero

that defines the system’s transient response. The load

pole is a dynamic pole, shifting the pole frequency with

changes in load. As the load decreases, the pole fre-

quency shifts to the left. System stability requires that

the compensation zero must be placed properly to

ensure adequate phase margin (at least 30° at unity

gain). The following is a design procedure for the com-

pensation network:

1) Select an appropriate converter bandwidth (fC) to

stabilize the system while maximizing transient

response. This bandwidth should not exceed 1/5 of

the switching frequency. Use 100kHz as a reason-

able starting point.

2) Calculate the compensation capacitor, C1, based

on this bandwidth:

C1

=

⎛

⎜

⎝

VO(MAX)

IO(MAX)

⎞

⎟

⎠

⎛

⎝⎜

1

RCS

⎞

⎠⎟

⎛

⎝⎜

gm

×

R2

R1+R2

⎞

⎠⎟

⎛

⎝⎜

2

×

1

π×

fC

⎞

⎠⎟

Resistors R1 and R2 are internal to the MAX1820; use

R1 = 151kΩ and R2 = 199kΩ as nominal values for cal-

culations. These resistors are external to the MAX1821

(see the Setting the Output Voltage section). Using

VOMAX = 3.4V, IOMAX = 0.6A, gm = 50µs, RCS = 0.75Ω,

C1 is evaluated as:

TIONC31

=

⎛

⎝⎜

3.4V

0.6A

⎞

⎠⎟

⎛

⎝⎜

1

0.75Ω

⎞

⎠⎟

⎛

⎝⎜

50µs

×

199kΩ

151kΩ +199kΩ

⎞

⎠⎟

×

⎛

⎝⎜

2

×

3.14

1

×

100kHz

⎞

⎠⎟

=

341pF

Selecting the nearest standard value of 330pF corre-

sponds to a 103kHz bandwidth, which is still accept-

able per the above criteria.

______________________________________________________________________________________ 13

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