MAX19527EXE 데이터 시트보기 (PDF) - Maxim Integrated
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MAX19527EXE
Maxim Integrated
MAX19527EXE Datasheet PDF : 30 Pages
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Ultra-Low-Power, Octal, 12-Bit, 50Msps,
1.8V ADC with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, internal reference, AIN = -0.5dBFS, differential clock, VCLKD = 1.5VP-P, fCLK = 50MHz, programmable
registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 9, Note 2)
SCLK Period
SCLK to CS Setup Time
SCLK to CS Hold Time
tSCLK
tCSS
tCSH
SDIO to SCLK Setup Time
tSDS Serial-data write
SDIO to SCLK Hold Time
tSDH Serial-data write
SCLK to SDIO Output Data Delay tSDD Serial-data read
TIMING CHARACTERISTICS (Figures 6 and 7, Note 2)
MIN
TYP
MAX UNITS
50
ns
10
ns
10
ns
10
ns
0
ns
10
ns
Data Valid to CLKOUT Rise/Fall
tOD
tSAMPLE/ tSAMPLE/ tSAMPLE/
24 - 0.10 24 + 0.05 24 + 0.20
ns
CLKOUT Output-Width High
tCH
CLKOUT Output-Width Low
tCL
FRAME Rise to CLKOUT Rise
tDF
tSAMPLE/12
ns
tSAMPLE/12
ns
tSAMPLE/ tSAMPLE/ tSAMPLE/
24 - 0.10 24 + 0.05 24 + 0.20
ns
Sample CLK Rise to Frame Rise
tSF
tSAMPLE/ tSAMPLE/ tSAMPLE/
2 + 1.6 2 + 2.3 2 + 3.3
ns
POWER REQUIREMENTS
Analog Supply Voltage
VAVDD
1.7
1.8
1.9
V
Digital Output Supply Voltage
VOVDD
1.7
1.8
1.9
V
8 channels active
158
180
Analog Supply Current
Incremental channel power-down
IAVDD Nap mode
-18
mA
13
15
Sleep mode
0.35
0.5
8 channels active, external RLOAD = 100I
87
Digital Output Supply Current
Incremental channel power-down
IOVDD Nap mode
-7.4
mA
28
Sleep mode
< 0.1
8 channels active
440
Total Power Dissipation
Incremental channel power-down
PTD Nap mode
-46
mW
74
Sleep mode
0.8
Note 1: Specifications are 100% production tested at TA R +25NC. Specifications for TA < +25NC are guaranteed by design and
characterization.
Note 2: Specifications guaranteed by design and characterization.
5
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