MAX2830 데이터 시트보기 (PDF) - Maxim Integrated

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MAX2830

2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch

Maxim Integrated 

2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA,

and Rx/Tx/Antenna Diversity Switch

Pin Description

PIN

NAME

FUNCTION

1

VCCLNA LNA Supply Voltage

2 GNDRXLNA LNA Ground

3

B6

Receiver and Transmitter Gain-Control Logic-Input Bit 6

4

ANT1+ Antenna 1. Differential Input to LNA in Rx mode. Input is internally AC-coupled and matched to 100Ω

5

ANT1-

differential. Connect directly to a 2:1 balun.

6

B7

Receiver Gain-Control Logic-Input Bit 7

7

VCCPA Supply Voltage for Second Stage of Power Amplifier

8

B3

Receiver and Transmitter Gain-Control Logic-Input Bit 3

9

ANT2+ Antenna 2. Differential inputs to LNA in diversity Rx mode and to PA differential outputs in Tx mode.

10

ANT2-

Internally AC-coupled differential outputs and matched to 100Ω differential. Connect directly to a 2:1 balun.

11

B2

Receiver and Transmitter Gain-Control Logic-Input Bit 2

12

SHDN

Active-Low Shutdown and Standby Logic Input. See Table 32 for operating modes.

13

VCCTXPA Supply Voltage for First-Stage of PA and PA Driver

14

B5

Receiver and Transmitter Gain-Control Logic-Input Bit 5

15

CS

Active-Low Chip-Select Logic Input of 3-Wire Serial Interface (see Figure 3)

16

RSSI

RSSI, PA Power Detector or Temperature-Sensor Multiplexed Analog Output

17

VCCTXMX Transmitter Upconverter Supply Voltage

18

SCLK

Serial-Clock Logic Input of 3-Wire Serial Interface (see Figure 3)

19

DIN

Data Logic Input of 3-Wire Serial Interface (see Figure 3)

20

VCCPLL PLL and Registers Supply Voltage. Connect to the supply voltage to retain the register settings.

21 CLOCKOUT Reference Clock Buffer Output

22

LD

Lock-Detect Logic Output of Frequency Synthesizer. Output high indicates that the frequency synthesizer is

locked. Output programmable as CMOS or open-drain output. (See Tables 17 and 21.)

23

B1

Receiver and Transmitter Gain-Control Logic-Input Bit 1

24

CPOUT

Charge-Pump Output. Connect the frequency synthesizer’s loop filter between CPOUT and TUNE (see the

Block Diagram/Typical Operating Circuit).

25

VCCCP PLL Charge-Pump Supply Voltage

26

GNDCP Charge-Pump Circuit Ground

27

VCCXTAL Crystal Oscillator Supply Voltage

28

XTAL

Crystal or Reference Clock Input. AC-couple a crystal or a reference clock to this analog input.

29

CTUNE

Connection for Crystal Oscillator Off-Chip Capacitors. When using an external reference clock input, leave

CTUNE unconnected.

30

VCCVCO VCO Supply Voltage

31

GNDVCO VCO Ground

32

TUNE

VCO TUNE Input (see the Block Diagram/Typical Operating Circuit)

33

BYPASS

On-Chip VCO Regulator Output Bypass. Bypass with a 0.1µF to 1µF capacitor to GND. Do not connect

other circuitry to this point.

34

B4

Receiver and Transmitter Gain-Control Logic-Input Bit 4

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