MAX9939 데이터 시트보기 (PDF) - Maxim Integrated

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MAX9939

SPI Programmable-Gain Amplifier with Input VOS Trim and Output Op Amp

Maxim Integrated 

SPI Programmable-Gain Amplifier

with Input VOS Trim and Output Op Amp

ELECTRICAL CHARACTERISTICS (continued)

(VCC = 5V, VGND = 0V, VINA+ = VINA-, Gain = 10V/V, ROUTA = ROUTB = 1kΩ to VCC/2, TA = TMIN to TMAX, unless otherwise noted.

Typical values are at TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Unity-Gain Bandwidth

UGBW

2.2

MHz

Slew Rate

SR

6.4

V/µs

Settling Time

Input-Voltage Noise Density

Distortion

Max Capacitive Load

tS

VN

THD

CL(MAX)

To 1%, 2V output step

f = 1kHz, VOUTA = 2.5VP-P, gain = -1V/V

0.86

µs

36

nV/√Hz

90

dB

1

nF

Output Swing

VOH, VOL

Voltage output high = VCC - VOUTB,

voltage output low = VOUTB - VGND

25

60

mV

POWER SUPPLY

Supply Voltage Range

Power-Supply Rejection Ratio

VCC Guaranteed by PSRR

2.9

5.5

V

1kΩ between OUTA and INB, 1kΩ between

PSRR OUTB and INB, measured differentially

60

80

dB

between OUTA and OUTB

Supply Current

Shutdown Supply Current

ICC

ISHDN

OUTA and OUTB unloaded

Soft shutdown through SPI

3.4

6.7

mA

13

24

µA

SPI CHARACTERISTICS

Input-Voltage Low

VIL

Input-Voltage High

VIH

VCC = 5V

VCC = 3.3V

Input Leakage Current

IIN

Input Capacitance

CIN

SPI TIMING CHARACTERISTICS

2.0

1.65

5

0.8

V

V

±1

µA

pF

SCLK Frequency

fSCLK (Note 5)

5

MHz

SCLK Period

SCLK Pulse-Width High

SCLK Pulse-Width Low

CS Fall to SCLK Rise Setup

tCP

tCH

tCL

tCSS

200

ns

80

ns

80

ns

80

ns

CS Fall to SCLK Rise Hold

tCSH

20 + (0.5

x tCP)

ns

DIN to SCLK Setup

DIN Hold after SCLK

SCLK Rise to CS Fall Delay

CS Rise to SCLK Rise Hold

CS Pulse-Width High

tDS

tDH

tCS0

tCS1

tCSW

55

ns

0

ns

20

ns

80

ns

200

ns

Note 1: All devices are 100% production tested at TA = +25°C. Temperature limits are guaranteed by design.

Note 2: The input offset voltage includes the effects of mismatches in the internal VCC/2 resistor dividers.

Note 3: For gain of 0.25V/V, the input common-mode range is -1V to VCC - 2V.

Note 4: The input current of a CMOS device is too low to be accurately measured on an ATE and is typically on the order of 1pA.

Note 5: Parts are functional with fSCLK = 10MHz.

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