MB89180L 데이터 시트보기 (PDF) - Fujitsu
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MB89180L Datasheet PDF : 48 Pages
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MB89180L Series
s BLOCK DIAGRAM
Main clock
X0
X1
Oscillator
(Max 4.2 MHz)
Subclock
X0A
X1A
Clock controller
Low-power oscillator
(32.768 kHz)
P00/INT20 8
to P07/INT27
21-bit timebase
timer
8 External interrupt 2
(wake-up function)
CMOS I/O port
P30/RCO
P31/COM2
P32/COM3
Remote control
transmission output
N-ch open-drain output port
(Only P30 for CMOS output port)
Reset circuit
RST
(Watchdog timer)
RAM
F2MC-8L
CPU
ROM
MODA
Vcc
Vss
Other pins
MODA
Vcc
Vss
N-ch open-drain I/O port
8-bit
timer/counter 1
(Timer 1)
8-bit
timer/counter 2
(Timer 2)
8-bit serial I/O
Buzzer output
CMOS I/O port
External interrupt 1 4
(wake-up function)
8
P26*2
P22/TO
P21*2
P20/EC
P25/SCK
P24/SO
P23/SI
P27*2/BUZ
4
P14 to P17
4 P10/INT10
to P13/INT13
4 SEG28*1 to SEG31*1
(also serve as P14 to P17)
4 SEG24*1 to SEG27*1
(also serve as P10 to P13)
LCD controller/driver
8
SEG0 to SEG7
2
COM0 to COM1
P31/COM2
P32/COM3
3
V1 to V3
32 × 4-bit display
RAM (16 bytes) 16
N-ch open-drain output port
4 P57/SEG23*1
to P54/SEG20*1
4 P53/SEG19*1
to P50/SEG16*1
4 P47/SEG15*1
to P44/SEG12*1
4 P43/SEG11*1
to P40/SEG8*1
*1: The segment or port function is selected by the mask option.
*2: N-ch open-drain heavy-current drive type.
20
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