MB91354A 데이터 시트보기 (PDF) - Fujitsu

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MB91354A

32-Bit Proprietary Microcontroller

Fujitsu 

MB91350A Series

■ MODE SETTINGS

The FR family uses mode pins (MD2 to MD0) and a mode register (MODR) to set the operation mode.

1. Mode Pins

The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed.

Mode Pins

MD2 MD1 MD0

Mode name

Reset vector

access area

Remarks

0 0 0 Internal ROM mode vector Internal

0 0 1 External ROM mode vector External The bus width is specified by the mode register.

Values other than those listed in the table are prohibited.

2. Mode Register (MODR)

The data written to the mode register at 000F FFF8H using mode vector fetch is called mode data.

After an operation mode has been set in the mode register (MODR), the device operates in the operation mode.

The mode register is set by any reset source. User programs cannot write data to the mode register.

Note : Conventionally the FR family has nothing at addresses (0000 07FFH) in the mode register.

<Register description>

MODR

7

6

5

4

3

2

1

0

Initial Value

000F FFF8H

0

0

0

0

0

ROMA WTH1 WTH0

XXXXXXXXB

Operation mode setting bits

[bit 7 to bit 3] Reserved bit

Be sure to set this bit to “00000”. Operation is not guaranteed when any value other than “00000” is set.

[bit 2] ROMA (internal ROM enable bit)

The ROMA bit is used to set whether to enable the internal F-bus RAM and F-bus ROM areas.

ROMA

function

Remarks

0

External ROM mode

Internal F-bus RAM is valid; the area (80000H to 100000H) of internal ROM is used

as an external area.

1 Internal ROM mode Internal F-bus RAM and F-bus ROM become valid.

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