MBM29LV080A-12PTN 데이터 시트보기 (PDF) - Fujitsu

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MBM29LV080A-12PTN

8M (1M x 8) BIT

Fujitsu 

MBM29LV080A-70/-90/-12

s AC CHARACTERISTICS

• Read Only Operations Characteristics

Parameter

Symbols

Description

JEDEC Standard

Test Setup

tAVAV

tRC Read Cycle Time

— Min.

tAVQV

tACC Address to Output Delay

CE = VIL

OE = VIL

Max.

tELQV

tCE Chip Enable to Output Delay

OE = VIL Max.

tGLQV

tOE Output Enable to Output Delay

— Max.

tEHQZ

tDF Chip Enable to Output HIGH-Z

— Max.

tGHQZ

tDF Output Enable to Output HIGH-Z

— Max.

tAXQX

tOH

Output Hold Time From Address,

CE or OE, Whichever Occurs First

—

Min.

—

tREADY RESET Pin Low to Read Mode

— Max.

-70

(Note)

70

70

70

30

25

25

0

20

-90

(Note)

90

90

90

35

30

30

0

20

Note: Test Conditions: Output Load: 1 TTL gate and 30 pF (MBM29LV080A-70)

1 TTL gate and 100 pF (MBM29LV080A-90/-12)

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output: 1.5 V

-12

(Note)

Unit

120 ns

120 ns

120 ns

50

ns

30

ns

30

ns

0

ns

20

µs

Device

Under

Test

CL

3.3 V

IN3064

or Equivalent

2.7 kΩ

6.2 kΩ

Diodes = IN3064

or Equivalent

Notes: CL = 30 pF including jig capacitance (MBM29LV080A-70)

CL = 100 pF including jig capacitance (MBM29LV080A-90/-12)

Figure 4 Test Conditions

25

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