MBM29LV800BE60PBT 데이터 시트보기 (PDF) - Fujitsu

부품명

상세내역

제조사

MBM29LV800BE60PBT

FLASH MEMORY CMOS 8 M (1 M × 8/512 K × 16) BIT

Fujitsu 

MBM29LV800TE/BE60/70/90

Write Operation Status

Hardware Sequence Flags

Status

Embedded Program Algorithm

Embedded Erase Algorithm

In Progress

Erase

Suspended

Mode

Erase Suspend Read

(Erase Suspended Sector)

Erase Suspend Read

(Non-Erase Suspended Sector)

Erase Suspend Program

(Non-Erase Suspended Sector)

Embedded Program Algorithm

Exceeded Embedded Erase Algorithm

Time Limits

Erase

Suspended

Mode

Erase Suspend Program

(Non-Erase Suspended Sector)

DQ7

DQ6

DQ5 DQ3

DQ2

DQ7 Toggle

0

0

1

0

Toggle

0

1

Toggle

1

1

0

0

Toggle

Data Data Data Data Data

DQ7 Toggle*1 0

0

1*2

DQ7 Toggle

1

0

1

0

Toggle

1

1

N/A

DQ7 Toggle

1

0

N/A

*1 : Performing successive read operations from any address will cause DQ6 to toggle.

*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”

at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.

Notes : • DQ1 and DQ0 are reserved pins for future use.

• DQ4 is Fujitsu internal use only.

DQ7

Data Polling

The MBM29LV800TE/BE devices feature Data Polling as a method to indicate to the host that the Embedded

Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read devices

will produce a complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm,

an attempt to read device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an

attempt to read device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm

an attempt to read device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in “Data

Polling Algorithm” in “s FLOW CHART”.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six

write pulse sequence. Data Polling must be performed at sector address of sectors being erased, not protected

sectors. Otherwise, the status may be invalid. Once the Embedded Algorithm operation is close to completion,

MBM29LV800TE/BE data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low.

This means that devices are driving status information on DQ7 at one instant of time and then that byte’s valid

data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status

or valid data. Even if device has completed the Embedded Algorithm operation and DQ7 has a valid data, data

outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will be read on the successive read

attempts.

The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm

or sector erase time-out.

See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “s TIMING DIAGRAM” for the

Data Polling timing specifications and diagrams.

22

Share Link: