MBM29LV800BE60PBT 데이터 시트보기 (PDF) - Fujitsu

부품명

상세내역

제조사

MBM29LV800BE60PBT

FLASH MEMORY CMOS 8 M (1 M × 8/512 K × 16) BIT

Fujitsu 

MBM29LV800TE/BE60/70/90

Byte/Word Configuration

BYTE pin selects byte (8-bit) mode or word (16-bit) mode for MBM29LV800TE/BE devices. When this pin is

driven high, devices operate in word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this

pin is driven low, devices operates in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest

address bit, and DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation

and hence commands are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Refer to “Timing Diagram

for Word Mode Configuration”, “Timing Diagram for Byte Mode Configuration” and “BYTE Timing Diagram for

Write Operations” in “s TIMING DIAGRAM” for the timing diagram.

Data Protection

MBM29LV800TE/BE are designed to offer protection against accidental erasure or programming caused by

spurious system level signals that may exist during power transitions. During power up, devices automatically

reset internal state machine in Read mode. Also, with its control register architecture, alteration of memory

contents only occurs after successful completion of specific multi-bus cycle command sequences.

Devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and

power-down transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less

than VLKO (Min) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are

disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until

the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct

to prevent unintentional writes when VCC is above VLKO (Min) .

If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle, CE and WE

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

25

Share Link: