MC100EP195FAG(2014) 데이터 시트보기 (PDF) - ON Semiconductor

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MC100EP195FAG
(Rev.:2014)

3.3V ECL Programmable Delay Chip

ON Semiconductor 

MC10EP195, MC100EP195

IN

IN

Q

Q

tPLH

VINPP = VIH(D) − VIL(D)

VOUTPP = VOH(Q) − VOL(Q)

tPHL

Figure 5. AC Reference Measurement

Cascading Multiple EP195s

To increase the programmable range of the EP195,

internal cascade circuitry has been included. This circuitry

allows for the cascading of multiple EP195s without the

need for any external gating. Furthermore, this capability

requires only one more address line per added E195.

Obviously, cascading multiple programmable delay chips

will result in a larger programmable range: however, this

increase is at the expense of a longer minimum delay.

Figure 6 illustrates the interconnect scheme for cascading

two EP195s. As can be seen, this scheme can easily be

expanded for larger EP195 chains. The D10 input of the

EP195 is the CASCADE control pin. With the interconnect

scheme of Figure 6 when D10 is asserted, it signals the need

for a larger programmable range than is achievable with a

single device and switches output pin CASCADE HIGH and

pin CASCADE LOW. The A11 address can be added to

generate a cascade output for the next EP195. For a 2−device

configuration, A11 is not required.

Need if Chip #3 is used

ADDRESS BUS

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

INPUT

D7 D6 D5 D4 VEE D3 D2 D1

D8

VEE

D9

D0

D10

VCC

IN

EP195

Q

IN

Q

VBB

CHIP #2

VCC

VEF

VCC

VCF

NC

D7 D6 D5 D4 VEE

D8

D9

D10

IN

EP195

D3 D2 D1

VEE

D0

VCC

Q

IN

Q

VBB

CHIP #1

VCC

VEF

VCC

VCF

NC

OUTPUT

Figure 6. Cascading Interconnect Architecture

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