MC100EP195FA 데이터 시트보기 (PDF) - ON Semiconductor
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MC100EP195FA Datasheet PDF : 20 Pages
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MC10EP195, MC100EP195
Table 12. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 20)
−40°C
25°C
85°C
Symbol
Characteristic
fmax
Maximum Frequency
tPLH
Propagation Delay
tPHL
IN to Q; D(0−10) = 0
IN to Q; D(0−10) = 1023
EN to Q; D(0−10) = 0
D0 to CASCADE
Min
1650
9500
1600
300
Typ Max Min Typ Max Min Typ Max Unit
1.2
1.2
1.2
GHz
ps
2050 2450 1800 2200 2600 1950 2350 2750
11500 13500 10000 12200 14000 10800 13300 15800
2150 2600 1800 2300 2800 2000 2500 3000
420 500 350 450 550 425 525 625
tRANGE Programmable Range
ps
tPD (max) − tPD (min) 7850 9450
8200 10000
8850 10950
Dt
Step Delay (Note 21)
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
13
27
44
90
130
312
590
1100
2250
4500
14
30
47
97
140
335
650
1180
2400
4800
ps
41
100
145
360
690
1300
2650
5300
mono Monotonicity (Note 27)
TBD
tSKEW Duty Cycle Skew (Note 22)
ps
|tPHL−tPLH|
25
25
25
ts
Setup Time
ps
D to LEN 200
0
200
0
200
0
D to IN (Note 23) 300 140
300 160
300 180
EN to IN (Note 24) 300 150
300 170
300 180
th
Hold Time
ps
LEN to D 200 60
200 100
200 80
IN to EN (Note 25) 400 250
400 280
400 300
tR
Release Time
ps
EN to IN (Note 26) 150 −25
150 −75
150 −50
SET MAX to LEN 400 200
400 250
400 300
SET MIN to LEN 350 275
350 200
350 225
tjitter
RMS Random Clock Jitter @ 1.2 GHz
IN to Q; D(0:10) = 0 or SETMIN
0.86
IN to Q; D(0:10) = 1023 or SETMAX
0.89
1.16
1.09
ps
1.12
1.02
VPP
Input Voltage Swing
(Differential Configuration)
150 800 1200 150 800 1200 150 800 1200 mV
tr
Output Rise/Fall Time @ 50 MHz
ps
tf
20−80% (Q) 85 100 135 85 110 135 95 125 155
20−80% (CASCADE) 100 140 200 110 150 200 130 170 220
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
21. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
22. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
23. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
24. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
±75 mV to that IN/IN transition.
25. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than ±75 mV to that IN/IN transition.
26. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
27. The monotonicity indicates the increasing delay value for each binary count increment on the control inputs D[9:0].
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