MC100EP195FA 데이터 시트보기 (PDF) - ON Semiconductor
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MC100EP195FA Datasheet PDF : 20 Pages
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MC10EP195, MC100EP195
Multi−Channel Deskewing
The most practical application for EP195 is in multiple
channel delay matching. Slight differences in impedance and
cable length can create large timing skews within a high−speed
system. To deskew multiple signal channels, each channel can
be sent through each EP195 as shown in Figure 8. One signal
channel can be used as reference and the other EP195s can be
used to adjust the delay to eliminate the timing skews. Nearly
any high−speed system can be fine−tuned (as small as 10 ps)
to reduce the skew to extremely tight tolerances.
EP195
IN
Q
IN
Q
#1
EP195
IN
Q
IN
Q
#2
Control
Logic
IN
IN
Digital
Data
EP195
Q
Q
#N
Figure 8. Multiple Channel Deskewing Diagram
Measure Unknown High Speed Device Delays
EP195s provide a possible solution to measure the
unknown delay of a device with a high degree of precision.
By combining two EP195s and EP31 as shown in Figure 9,
the delay can be measured. The first EP195 can be set to
SETMIN and its output is used to drive the unknown delay
device, which in turn drives the input of a D flip−flop of
EP31. The second EP195 is triggered along with the first
EP195 and its output provides a clock signal for EP31.
The programmed delay of the second EP195 is varied to
detect the output edge from the unknown delay device.
If the programmed delay through the second EP195 is too
long, the flip−flop output will be at logic high. On the other
hand, if the programmed delay through the second EP195 is
too short, the flip−flop output will be at a logic low. If the
programmed delay is correctly fine−tuned in the second
EP195, the flip−flop will bounce between logic high and logic
low. The digital code in the second EP195 can be directly
correlated into an accurate device delay.
CLOCK
CLOCK
EP195
IN
Q
IN
Q
#1
EP195
IN
Q
IN
Q
#2
Unknown Delay
Device
D
Q
EP31
CLK
Q
Control
Logic
Figure 9. Multiple Channel Deskewing Diagram
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